From patchwork Tue May 10 12:11:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67449 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp2093032qge; Tue, 10 May 2016 05:16:57 -0700 (PDT) X-Received: by 10.140.37.35 with SMTP id q32mr40760301qgq.17.1462882617913; Tue, 10 May 2016 05:16:57 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id x13si1216244qka.33.2016.05.10.05.16.57; Tue, 10 May 2016 05:16:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8700B61651; Tue, 10 May 2016 12:16:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 7AC9161647; Tue, 10 May 2016 12:13:59 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5C65C6165E; Tue, 10 May 2016 12:13:38 +0000 (UTC) Received: from mail-wm0-f43.google.com (mail-wm0-f43.google.com [74.125.82.43]) by lists.linaro.org (Postfix) with ESMTPS id B34C661663 for ; Tue, 10 May 2016 12:12:23 +0000 (UTC) Received: by mail-wm0-f43.google.com with SMTP id e201so175184995wme.0 for ; Tue, 10 May 2016 05:12:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hrjpcF7kmCPQ/AvC8ogTxUZRiw2iz0SwZQhGkquG2wg=; b=JShA3keHStA3eVJm2Hr7tnIY55TazSyZbfzn9i6uCRtWSREnlSnMGV/TsAY7byVKeq IHyR3Pje5D9+fMa63G8fLs0APB7Sf+AW3Z9s93uCo5XYpgSf5lI/BptnYRJ+23auBHnf ITyj8iwC0HUjlBs0vNdG/+Zcs2kpp/P5IUnOzgGZsdT2JNsbZzoM2LAedKMWovmBWTqF q0PEY47ZSiBUkH7SUUjy2nKMWuzrw8hgT0O1VJKS765uyCZUx4MCrV104N97JOHNARKW q0MLg95NQP6YcdaziNE5FggbFisuAGchhlrHvpcbUJXAHLwdCVrrd1KaA6Q7PKFrIEj3 X7Aw== X-Gm-Message-State: AOPr4FVaorS9CTDfQCiDfY/lgd+I7fj3izBZUhvBM7tn/LA0rvNXLsjfcWC+jTjdzP8EC1/uwZc= X-Received: by 10.28.213.137 with SMTP id m131mr17211138wmg.24.1462882342932; Tue, 10 May 2016 05:12:22 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id m20sm2623084wma.23.2016.05.10.05.12.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 10 May 2016 05:12:22 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Tue, 10 May 2016 14:11:52 +0200 Message-Id: <1462882313-7637-14-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462882313-7637-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462882313-7637-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 13/14] Platforms/AMD/Styx: reallocate the in-memory copy of the varstore FV X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Before the DXE core has a chance to overwrite the in-memory copy of the varstore FV, relocate it to a dynamically allocated buffer. Note that, while this allocation is not made from the temporary PEI heap, the bookkeeping involved in calling AllocateAlignedRuntimePages() appears to push the envelope slightly, and so we need to increase the initial stack size (which is actually stack + heap) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 6 ++- Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c | 41 ++++++++++++++++++++ Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 9 +++++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 6 ++- 4 files changed, 60 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 98e08ba90828..52b891d9d1e4 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -400,7 +400,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x6000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 # Stacks for MPCores in Monitor Mode @@ -524,6 +524,10 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000 gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 + ################################################################################ # # Components Section - list of all EDK II Modules needed by this Platform diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index ac172fa526c5..77116274c770 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,44 @@ InitMmu ( } } +STATIC +VOID +MoveNvStoreImage ( + VOID + ) +{ + VOID *OldBase, *NewBase; + UINTN Size; + + // + // Move the in-memory image of the NV store firmware volume to a dynamically + // allocated buffer. This gets rid of the annoying static memory reservation + // at the base of memory where all other UEFI allocations are near the top. + // + OldBase = (VOID *)FixedPcdGet64 (PcdFlashNvStorageOriginalBase); + + Size = FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize); + + NewBase = AllocateAlignedRuntimePages (EFI_SIZE_TO_PAGES (Size), SIZE_64KB); + ASSERT (NewBase != NULL); + + CopyMem (NewBase, OldBase, Size); + + DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n", + __FUNCTION__, OldBase, NewBase)); + + PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase); + + PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase + + FixedPcdGet32 (PcdFlashNvStorageVariableSize)); + + PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase + + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)); +} + /*++ Routine Description: @@ -144,5 +183,7 @@ MemoryPeim ( BuildMemoryTypeInformationHob (); } + MoveNvStoreImage (); + return EFI_SUCCESS; } diff --git a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index adacd700083c..0201964003d0 100644 --- a/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Platforms/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -78,9 +78,18 @@ gAmdStyxTokenSpaceGuid.PcdIscpSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gAmdStyxTokenSpaceGuid.PcdFlashNvStorageOriginalBase + [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + [Depex] gAmdStyxPlatInitPpiGuid diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index d069851b5c93..a1a755180da0 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -404,7 +404,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x6000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 # Stacks for MPCores in Monitor Mode @@ -549,6 +549,10 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0x02B1B2B3B4B5 !endif + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 + ################################################################################ #