From patchwork Wed May 11 16:00:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67596 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp309227qge; Wed, 11 May 2016 09:16:58 -0700 (PDT) X-Received: by 10.55.164.76 with SMTP id n73mr4530447qke.78.1462983418768; Wed, 11 May 2016 09:16:58 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id u78si5688113qge.68.2016.05.11.09.16.58; Wed, 11 May 2016 09:16:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6C1C861650; Wed, 11 May 2016 16:16:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 376516164F; Wed, 11 May 2016 16:03:44 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 399006166D; Wed, 11 May 2016 16:03:41 +0000 (UTC) Received: from mail-wm0-f49.google.com (mail-wm0-f49.google.com [74.125.82.49]) by lists.linaro.org (Postfix) with ESMTPS id 00F8B6164F for ; Wed, 11 May 2016 16:01:06 +0000 (UTC) Received: by mail-wm0-f49.google.com with SMTP id a17so90960364wme.0 for ; Wed, 11 May 2016 09:01:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wfGokUUI6g9acoa5S+Ic5ySJwgDZ3kHZyequVneJJWo=; b=IvS6BA6sLCbeWz8CAWVIElLQ2/am0SnIhClcdAJGgwqamRUBtYbVVQRq+rB4cULCCF uy6zHhLVTVIO6mbAp/63THRU1LvBiFkYN6B7y3C26ZPVOv5FKcqvbhsuwAt6yK4L8IX/ LFdr6IQtGEK4vWV/fFEtWT8dY89UnMSHU1Hhk8Nm05WnUdme/7EtcZlJCj/LnwqET3DB lhZhjSK6009wy23Mr7yJs7TcfLlk63mDfTPBvyR7RDBo7swgM/YLQJBVTM187vcHhqmh IWDBQKHR8lEd3ZXeW1pd/70JY9PTFehBTy/ZJB/JaPqyVaAJQ4yTMklxbRpdISsDexp/ SnIg== X-Gm-Message-State: AOPr4FV94PiTnVnG+mZRb2lvE4bVEYedbBKM38sLRKoAZru7LNUwkIGc0TXhTE47wFFFGKIr3+4= X-Received: by 10.28.7.197 with SMTP id 188mr911198wmh.101.1462982465065; Wed, 11 May 2016 09:01:05 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id f11sm36699133wmf.22.2016.05.11.09.01.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 May 2016 09:01:04 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Wed, 11 May 2016 18:00:42 +0200 Message-Id: <1462982452-1316-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462982452-1316-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462982452-1316-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 01/11] Platforms/AMD/Styx/AmdStyxPciHostBridgeLib: set unused regions base to MAX_UINT64 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" An upcoming fix to the generic PciHostBridgeDxe driver code requires that the limit of an unused region does not exceed the base, since they describe a 1 byte region if base equals limit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c index 432e4230a59b..8d8c76a0f7f6 100644 --- a/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c +++ b/Platforms/AMD/Styx/Library/AmdStyxPciHostBridgeLib/AmdStyxPciHostBridgeLib.c @@ -106,9 +106,9 @@ PciHostBridgeGetRootBridges ( // // No separate ranges for prefetchable and non-prefetchable BARs // - RootBridge->PMem.Base = 0; + RootBridge->PMem.Base = MAX_UINT64; RootBridge->PMem.Limit = 0; - RootBridge->PMemAbove4G.Base = 0; + RootBridge->PMemAbove4G.Base = MAX_UINT64; RootBridge->PMemAbove4G.Limit = 0; ASSERT (FixedPcdGet64 (PcdPciMmio32Translation) == 0);