| Message ID | 20230421223147.115156-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | e035ddb68bb2827cff3aad1a6ff17ecc6e62f07e |
| Headers | show |
| Series | arm64: dts: socionext: add missing cache properties | expand |
Hi Krzysztof, Thank you for your patch. I'll take this when updating the devicetree for next. Thank you, On 2023/04/22 7:31, Krzysztof Kozlowski wrote: > As all level 2 and level 3 caches are unified, add required > cache-unified and cache-level properties to fix warnings like: > > uniphier-ld11-ref.dtb: l2-cache: 'cache-level' is a required property > uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Please take the patch via sub-arch SoC tree. > --- > arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 ++ > arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 4 ++++ > arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++ > 3 files changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > index 7bb36b071475..4680571c264d 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi > @@ -52,6 +52,8 @@ cpu1: cpu@1 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > + cache-unified; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > index 4e2171630272..335093da6573 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi > @@ -86,10 +86,14 @@ cpu3: cpu@101 { > > a72_l2: l2-cache0 { > compatible = "cache"; > + cache-level = <2>; > + cache-unified; > }; > > a53_l2: l2-cache1 { > compatible = "cache"; > + cache-level = <2>; > + cache-unified; > }; > }; > > diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > index 38ccfb46ea42..d6e3cc6fdb25 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi > @@ -83,6 +83,8 @@ cpu3: cpu@3 { > > l2: l2-cache { > compatible = "cache"; > + cache-level = <2>; > + cache-unified; > }; > }; > --- Best Regards Kunihiko Hayashi
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b071475..4680571c264d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,8 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272..335093da6573 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,14 @@ cpu3: cpu@101 { a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea42..d6e3cc6fdb25 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,8 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; };
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: uniphier-ld11-ref.dtb: l2-cache: 'cache-level' is a required property uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 ++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 4 ++++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++ 3 files changed, 8 insertions(+)