From patchwork Sat May 14 20:40:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67811 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp859392qge; Sat, 14 May 2016 13:40:24 -0700 (PDT) X-Received: by 10.66.221.167 with SMTP id qf7mr33293488pac.94.1463258424045; Sat, 14 May 2016 13:40:24 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 16si33308492pfb.78.2016.05.14.13.40.23; Sat, 14 May 2016 13:40:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753919AbcENUkW (ORCPT + 4 others); Sat, 14 May 2016 16:40:22 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:35156 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753810AbcENUkV (ORCPT ); Sat, 14 May 2016 16:40:21 -0400 Received: by mail-wm0-f50.google.com with SMTP id e201so59104565wme.0 for ; Sat, 14 May 2016 13:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WGZy3cm7lmmDq35V/9s25tPq8eEYSHyd4UV0w1aLNsw=; b=aq5vPenXVaA8LAnYiWgfcBGxI1jzvcncD6+i74WXaZo2Ww9QJfBSE0tU/rYHivWhZi xCbJXTZkEXh+KnHT/lbdxyNPezl2PzszR11NtaROnfwDxjL3Z8nPeMANIIjBN2Hnqb+5 nVYypfugcbdq752vbQss2UAQqDI44yTdCOInk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WGZy3cm7lmmDq35V/9s25tPq8eEYSHyd4UV0w1aLNsw=; b=MZykD5qWv4zALPuke7f1vuEZ7+1XrYfyibt/oAi43hhhVifaJU9MfhoDd39ECXEPAS 49PZj8fweP1nLseZrPojLhqCR6C+zPDMTjhwRJ/t3O3PYR2ncMoj/ii9o/h7jja1R47L dYdo/jVx+IqJwZs1RUZJY4StfGABePu7QfFOUcS+NfxckPt1sHJdMVXRcdSMDEUTbeAB 52oWwVGwa7n6HvvDvMeR2urKlHutRyQJ55k5rSwwErVkJYnExni5oWoUotFFzEta2SVc kKAkeDNm9wTGtKdTnF7LAPFTattDGS/ZL1q4TiMvwDGRsKanxwWwwj/6kXzRnd9TsD81 ZJhw== X-Gm-Message-State: AOPr4FUVgYMDiZB0g3M58BCRd/Gv20c1hMHNX0rEaaoxqvbTciQDmrcFnHs/ntJW0EYFAA9j X-Received: by 10.194.249.36 with SMTP id yr4mr25245765wjc.59.1463258419686; Sat, 14 May 2016 13:40:19 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id ib1sm25247720wjb.48.2016.05.14.13.40.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 14 May 2016 13:40:18 -0700 (PDT) From: Ard Biesheuvel To: netdev@vger.kernel.org, romieu@fr.zoreil.com Cc: ricardo.salveti@linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, amit.kucheria@linaro.org, davem@davemloft.net, Ard Biesheuvel , Realtek linux nic maintainers Subject: [PATCH v2] r8169: default to 64-bit DMA on recent PCIe chips Date: Sat, 14 May 2016 22:40:15 +0200 Message-Id: <1463258415-31072-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The current logic around the 'use_dac' module parameter prevents the r81969 driver from being loadable on 64-bit systems without any RAM below 4 GB when the parameter is left at its default value. So introduce a new default value -1 which indicates that 64-bit DMA should be enabled on sufficiently recent PCIe chips, i.e., versions RTL_GIGA_MAC_VER_18 or later. Explicit param values of 0 or 1 retain the existing behavior of unconditionally enabling/disabling 64-bit DMA on 64-bit architectures (i.e., regardless of the type and version of the chip) Since PCIe chips do not need to CPlusCmd Dual Address Cycle to be set, make that conditional on the device type as well. Cc: Realtek linux nic maintainers Signed-off-by: Ard Biesheuvel --- This is a followup to 'r8169: default to 64-bit DMA on systems without memory below 4 GB' [1]. At the request of Francois, this version bases the decision whether to use 64-bit DMA by default on whether the device is PCIe and sufficiently recent, rather than whether the platform requires 64-bit DMA because it does not have any memory below 4 GB to begin with. This is safer, since it will prevent the use of such problematic cards on these platforms. v2: drop unnecessary reordering of rtl8169_get_mac_version() call with pcie check [1] http://article.gmane.org/gmane.linux.network/412246 drivers/net/ethernet/realtek/r8169.c | 44 +++++++++++--------- 1 file changed, 25 insertions(+), 19 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 94f08f1e841c..0e62d74b09b3 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -345,7 +345,7 @@ static const struct pci_device_id rtl8169_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); static int rx_buf_sz = 16383; -static int use_dac; +static int use_dac = -1; static struct { u32 msg_enable; } debug = { -1 }; @@ -8224,20 +8224,6 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_out_mwi_2; } - tp->cp_cmd = 0; - - if ((sizeof(dma_addr_t) > 4) && - !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { - tp->cp_cmd |= PCIDAC; - dev->features |= NETIF_F_HIGHDMA; - } else { - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (rc < 0) { - netif_err(tp, probe, dev, "DMA configuration failed\n"); - goto err_out_free_res_3; - } - } - /* ioremap MMIO region */ ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); if (!ioaddr) { @@ -8253,6 +8239,25 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) /* Identify chip attached to board */ rtl8169_get_mac_version(tp, dev, cfg->default_ver); + tp->cp_cmd = 0; + + if ((sizeof(dma_addr_t) > 4) && + (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) && + tp->mac_version >= RTL_GIGA_MAC_VER_18)) && + !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + + /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */ + if (!pci_is_pcie(pdev)) + tp->cp_cmd |= PCIDAC; + dev->features |= NETIF_F_HIGHDMA; + } else { + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (rc < 0) { + netif_err(tp, probe, dev, "DMA configuration failed\n"); + goto err_out_unmap_4; + } + } + rtl_init_rxcfg(tp); rtl_irq_disable(tp); @@ -8412,12 +8417,12 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) &tp->counters_phys_addr, GFP_KERNEL); if (!tp->counters) { rc = -ENOMEM; - goto err_out_msi_4; + goto err_out_msi_5; } rc = register_netdev(dev); if (rc < 0) - goto err_out_cnt_5; + goto err_out_cnt_6; pci_set_drvdata(pdev, dev); @@ -8451,12 +8456,13 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) out: return rc; -err_out_cnt_5: +err_out_cnt_6: dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters, tp->counters_phys_addr); -err_out_msi_4: +err_out_msi_5: netif_napi_del(&tp->napi); rtl_disable_msi(pdev, tp); +err_out_unmap_4: iounmap(ioaddr); err_out_free_res_3: pci_release_regions(pdev);