| Message ID | 48b554aef75d11e6ad2ef7d21f22accb35432112.1683034376.git.michal.simek@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: zynqmp: Misc zynqmp changes | expand |
On 5/2/23 15:35, Michal Simek wrote: > bootph-all as phase tag was added to dt-schema > (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. > That's why add it also to Linux to be aligned with bootloader requirement. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > --- > arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 ++++++ > arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ > 3 files changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > index 581221fdadf1..719ea5d5ae88 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > @@ -11,30 +11,35 @@ > #include <dt-bindings/clock/xlnx-zynqmp-clk.h> > / { > pss_ref_clk: pss_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <33333333>; > }; > > video_clk: video_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <27000000>; > }; > > pss_alt_ref_clk: pss_alt_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <0>; > }; > > gt_crx_ref_clk: gt_crx_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <108000000>; > }; > > aux_ref_clk: aux_ref_clk { > + bootph-all; > compatible = "fixed-clock"; > #clock-cells = <0>; > clock-frequency = <27000000>; > @@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk { > > &zynqmp_firmware { > zynqmp_clk: clock-controller { > + bootph-all; > #clock-cells = <1>; > compatible = "xlnx,zynqmp-clk"; > clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > index 78ff6a9b3144..8afdf4408a78 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > @@ -243,17 +243,20 @@ tpm@0 { /* slm9670 - U144 */ > > &i2c1 { > status = "okay"; > + bootph-all; > clock-frequency = <400000>; > scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; > sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; > > eeprom: eeprom@50 { /* u46 - also at address 0x58 */ > + bootph-all; > compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ > reg = <0x50>; > /* WP pin EE_WP_EN connected to slg7x644092@68 */ > }; > > eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ > + bootph-all; > compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ > reg = <0x51>; > }; > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index d01d4334c95f..51b8349dcacd 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -127,6 +127,7 @@ rproc_1_fw_image: memory@3ef00000 { > }; > > zynqmp_ipi: zynqmp_ipi { > + bootph-all; > compatible = "xlnx,zynqmp-ipi-mailbox"; > interrupt-parent = <&gic>; > interrupts = <0 35 4>; > @@ -136,6 +137,7 @@ zynqmp_ipi: zynqmp_ipi { > ranges; > > ipi_mailbox_pmu1: mailbox@ff9905c0 { > + bootph-all; > reg = <0x0 0xff9905c0 0x0 0x20>, > <0x0 0xff9905e0 0x0 0x20>, > <0x0 0xff990e80 0x0 0x20>, > @@ -152,6 +154,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { > dcc: dcc { > compatible = "arm,dcc"; > status = "disabled"; > + bootph-all; > }; > > pmu { > @@ -177,8 +180,10 @@ zynqmp_firmware: zynqmp-firmware { > compatible = "xlnx,zynqmp-firmware"; > #power-domain-cells = <1>; > method = "smc"; > + bootph-all; > > zynqmp_power: zynqmp-power { > + bootph-all; > compatible = "xlnx,zynqmp-power"; > interrupt-parent = <&gic>; > interrupts = <0 35 4>; > @@ -258,6 +263,7 @@ r5f-1 { > > amba: axi { > compatible = "simple-bus"; > + bootph-all; > #address-cells = <2>; > #size-cells = <2>; > ranges; > @@ -699,6 +705,7 @@ pcie_intc: legacy-interrupt-controller { > }; > > qspi: spi@ff0f0000 { > + bootph-all; > compatible = "xlnx,zynqmp-qspi-1.0"; > status = "disabled"; > clock-names = "ref_clk", "pclk"; > @@ -745,6 +752,7 @@ sata: ahci@fd0c0000 { > }; > > sdhci0: mmc@ff160000 { > + bootph-all; > compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -759,6 +767,7 @@ sdhci0: mmc@ff160000 { > }; > > sdhci1: mmc@ff170000 { > + bootph-all; > compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -851,6 +860,7 @@ ttc3: timer@ff140000 { > }; > > uart0: serial@ff000000 { > + bootph-all; > compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -861,6 +871,7 @@ uart0: serial@ff000000 { > }; > > uart1: serial@ff010000 { > + bootph-all; > compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; > status = "disabled"; > interrupt-parent = <&gic>; > @@ -982,6 +993,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { > }; > > zynqmp_dpsub: display@fd4a0000 { > + bootph-all; > compatible = "xlnx,zynqmp-dpsub-1.7"; > status = "disabled"; > reg = <0x0 0xfd4a0000 0x0 0x1000>, Applied. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 581221fdadf1..719ea5d5ae88 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -11,30 +11,35 @@ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { pss_ref_clk: pss_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { + bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -43,6 +48,7 @@ aux_ref_clk: aux_ref_clk { &zynqmp_firmware { zynqmp_clk: clock-controller { + bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 78ff6a9b3144..8afdf4408a78 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -243,17 +243,20 @@ tpm@0 { /* slm9670 - U144 */ &i2c1 { status = "okay"; + bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ + bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index d01d4334c95f..51b8349dcacd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -127,6 +127,7 @@ rproc_1_fw_image: memory@3ef00000 { }; zynqmp_ipi: zynqmp_ipi { + bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -136,6 +137,7 @@ zynqmp_ipi: zynqmp_ipi { ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { + bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, @@ -152,6 +154,7 @@ ipi_mailbox_pmu1: mailbox@ff9905c0 { dcc: dcc { compatible = "arm,dcc"; status = "disabled"; + bootph-all; }; pmu { @@ -177,8 +180,10 @@ zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; + bootph-all; zynqmp_power: zynqmp-power { + bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; @@ -258,6 +263,7 @@ r5f-1 { amba: axi { compatible = "simple-bus"; + bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; @@ -699,6 +705,7 @@ pcie_intc: legacy-interrupt-controller { }; qspi: spi@ff0f0000 { + bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -745,6 +752,7 @@ sata: ahci@fd0c0000 { }; sdhci0: mmc@ff160000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -759,6 +767,7 @@ sdhci0: mmc@ff160000 { }; sdhci1: mmc@ff170000 { + bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; @@ -851,6 +860,7 @@ ttc3: timer@ff140000 { }; uart0: serial@ff000000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -861,6 +871,7 @@ uart0: serial@ff000000 { }; uart1: serial@ff010000 { + bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; @@ -982,6 +993,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { }; zynqmp_dpsub: display@fd4a0000 { + bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>,
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. Signed-off-by: Michal Simek <michal.simek@amd.com> --- --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++++++++ 3 files changed, 21 insertions(+)