| Message ID | 20230503070656.1746170-48-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Improve atomicity support | expand |
On Wed, 3 May 2023 at 08:41, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/mips/tcg-target.c.inc | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index cd0254a0d7..43a8ffac17 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1139,6 +1139,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) > typedef struct { > TCGReg base; > MemOp align; > + MemOp atom; > } HostAddress; > > bool tcg_target_has_memory_bswap(MemOp memop) > @@ -1158,11 +1159,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, > { > TCGLabelQemuLdst *ldst = NULL; > MemOp opc = get_memop(oi); > - unsigned a_bits = get_alignment_bits(opc); > + MemOp a_bits, atom_u; > unsigned s_bits = opc & MO_SIZE; > - unsigned a_mask = (1 << a_bits) - 1; > + unsigned a_mask; > TCGReg base; > > + a_bits = atom_and_align_for_opc(s, &h->atom, &atom_u, opc, > + MO_ATOM_IFALIGN, false); > + h->align = a_bits; > + a_mask = (1 << a_bits) - 1; > + > #ifdef CONFIG_SOFTMMU > unsigned s_mask = (1 << s_bits) - 1; > int mem_index = get_mmuidx(oi); Reviewed-by: Peter Maydell <peter.maydell@linaro.org> (For a set of functions so new they're not even in master yet these do seem to have a surprisingly large variance in how they're setting up these HostAddress structs...) thanks -- PMM
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index cd0254a0d7..43a8ffac17 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1139,6 +1139,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) typedef struct { TCGReg base; MemOp align; + MemOp atom; } HostAddress; bool tcg_target_has_memory_bswap(MemOp memop) @@ -1158,11 +1159,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, { TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); - unsigned a_bits = get_alignment_bits(opc); + MemOp a_bits, atom_u; unsigned s_bits = opc & MO_SIZE; - unsigned a_mask = (1 << a_bits) - 1; + unsigned a_mask; TCGReg base; + a_bits = atom_and_align_for_opc(s, &h->atom, &atom_u, opc, + MO_ATOM_IFALIGN, false); + h->align = a_bits; + a_mask = (1 << a_bits) - 1; + #ifdef CONFIG_SOFTMMU unsigned s_mask = (1 << s_bits) - 1; int mem_index = get_mmuidx(oi); @@ -1281,7 +1287,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #endif h->base = base; - h->align = a_bits; return ldst; }
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/mips/tcg-target.c.inc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)