diff mbox series

[16/23] arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2

Message ID ad019501a851c5730427af948b636316f10b2e3b.1683034376.git.michal.simek@amd.com
State New
Headers show
Series arm64: zynqmp: Misc zynqmp changes | expand

Commit Message

Michal Simek May 2, 2023, 1:35 p.m. UTC
From: Piyush Mehta <piyush.mehta@xilinx.com>

The board zynqmp-zc1751-xm016-dc2 support only USB2.0 that's why remove
USB3.0 DT configuration.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 --
 1 file changed, 2 deletions(-)

Comments

Michal Simek May 16, 2023, 11:08 a.m. UTC | #1
On 5/2/23 15:35, Michal Simek wrote:
> From: Piyush Mehta <piyush.mehta@xilinx.com>
> 
> The board zynqmp-zc1751-xm016-dc2 support only USB2.0 that's why remove
> USB3.0 DT configuration.
> 
> Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>   arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> index a2031187d9b3..9e7564235b69 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
> @@ -489,8 +489,6 @@ &usb1 {
>   &dwc3_1 {
>   	status = "okay";
>   	dr_mode = "host";
> -	snps,usb3_lpm_capable;
> -	maximum-speed = "super-speed";
>   };
>   
>   &uart0 {

Applied.
M
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
index a2031187d9b3..9e7564235b69 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -489,8 +489,6 @@  &usb1 {
 &dwc3_1 {
 	status = "okay";
 	dr_mode = "host";
-	snps,usb3_lpm_capable;
-	maximum-speed = "super-speed";
 };
 
 &uart0 {