diff mbox

[edk2,v2,5/7] OvmfPkg: determine PMBA value dependent on host bridge device ID

Message ID 1463498570-4469-6-git-send-email-lersek@redhat.com
State New
Headers show

Commit Message

Laszlo Ersek May 17, 2016, 3:22 p.m. UTC 
In this patch, the AcpiTimerLib instances, ResetSystemLib, and PlatformPei
are modified together in order to keep VMs functional across a bisection:
they all must agree on the PMBA value used.

ResetSystemLib must not use dynamic PCDs. With SOURCE_DEBUG_ENABLE, it
gets linked into the debug agent, therefore the same restrictions apply to
it as to BaseRomAcpiTimerLib. Luckily, AcpiPmControl() is only used for
powering off the virtual machine, thus the extra cost of a PCI config
space read, compared to a PcdGet16(), should be negligible.

This is the patch that moves the PMBA to IO port 0x0600 on Q35 in
practice.

The ResetSystemLib change is easiest to verify with the "reset -s" command
in the UEFI shell (which goes through gRT->ResetSystem() and, in OVMF,
PcAtChipsetPkg/KbcResetDxe).

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

---

Notes:
    v2:
    - use macros rather than fixed PCDs [Jordan]
    - update "BaseAcpiTimerLib.c" and "BaseRomAcpiTimerLib.c" comments in
      patch #1, not here

 OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c    |  8 ++++++-
 OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c |  8 ++++++-
 OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c    | 22 ++++++++++++++++++--
 OvmfPkg/PlatformPei/Platform.c                     |  8 ++++++-
 4 files changed, 41 insertions(+), 5 deletions(-)

-- 
1.8.3.1


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diff mbox

Patch

diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 652545d8647e..a839495e673d 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -32,31 +32,37 @@  STATIC UINT32 mAcpiTimerIoAddr;
 RETURN_STATUS
 EFIAPI
 AcpiTimerLibConstructor (
   VOID
   )
 {
   UINT16 HostBridgeDevId;
   UINTN Pmba;
+  UINT32 PmbaAndVal;
+  UINT32 PmbaOrVal;
   UINTN AcpiCtlReg;
   UINT8 AcpiEnBit;
 
   //
   // Query Host Bridge DID to determine platform type
   //
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
   switch (HostBridgeDevId) {
     case INTEL_82441_DEVICE_ID:
       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
+      PmbaOrVal  = PIIX4_PMBA_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
       break;
     case INTEL_Q35_MCH_DEVICE_ID:
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
+      PmbaOrVal  = ICH9_PMBASE_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
       break;
     default:
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
         __FUNCTION__, HostBridgeDevId));
       ASSERT (FALSE);
       return RETURN_UNSUPPORTED;
@@ -65,17 +71,17 @@  AcpiTimerLibConstructor (
   //
   // Check to see if the Power Management Base Address is already enabled
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program it now.
     //
-    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 
     //
     // Enable PMBA I/O port decodes
     //
     PciOr8 (AcpiCtlReg, AcpiEnBit);
   }
 
   mAcpiTimerIoAddr = (PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET;
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index 735dfd2e4bf9..dbbecc93c116 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -30,31 +30,37 @@ 
 RETURN_STATUS
 EFIAPI
 AcpiTimerLibConstructor (
   VOID
   )
 {
   UINT16 HostBridgeDevId;
   UINTN Pmba;
+  UINT32 PmbaAndVal;
+  UINT32 PmbaOrVal;
   UINTN AcpiCtlReg;
   UINT8 AcpiEnBit;
 
   //
   // Query Host Bridge DID to determine platform type
   //
   HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
   switch (HostBridgeDevId) {
     case INTEL_82441_DEVICE_ID:
       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
+      PmbaOrVal  = PIIX4_PMBA_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
       break;
     case INTEL_Q35_MCH_DEVICE_ID:
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
+      PmbaOrVal  = ICH9_PMBASE_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
       break;
     default:
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
         __FUNCTION__, HostBridgeDevId));
       ASSERT (FALSE);
       return RETURN_UNSUPPORTED;
@@ -63,17 +69,17 @@  AcpiTimerLibConstructor (
   //
   // Check to see if the Power Management Base Address is already enabled
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program it now.
     //
-    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 
     //
     // Enable PMBA I/O port decodes
     //
     PciOr8 (AcpiCtlReg, AcpiEnBit);
   }
 
   return RETURN_SUCCESS;
diff --git a/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c b/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c
index 308a6002149d..399f547d9185 100644
--- a/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c
+++ b/OvmfPkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -13,28 +13,46 @@ 
 **/
 
 #include <Base.h>
 
 #include <Library/BaseLib.h>
 #include <Library/DebugLib.h>
 #include <Library/IoLib.h>
 #include <Library/TimerLib.h>
+#include <OvmfPlatforms.h>
 
 #include <OvmfPlatforms.h>
 
 VOID
 AcpiPmControl (
   UINTN SuspendType
   )
 {
+  UINT16 AcpiPmBaseAddress;
+  UINT16 HostBridgeDevId;
+
   ASSERT (SuspendType < 6);
 
-  IoBitFieldWrite16 (PIIX4_PMBA_VALUE + 4, 10, 13, (UINT16) SuspendType);
-  IoOr16 (PIIX4_PMBA_VALUE + 4, BIT13);
+  AcpiPmBaseAddress = 0;
+  HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+  switch (HostBridgeDevId) {
+  case INTEL_82441_DEVICE_ID:
+    AcpiPmBaseAddress = PIIX4_PMBA_VALUE;
+    break;
+  case INTEL_Q35_MCH_DEVICE_ID:
+    AcpiPmBaseAddress = ICH9_PMBASE_VALUE;
+    break;
+  default:
+    ASSERT (FALSE);
+    CpuDeadLoop ();
+  }
+
+  IoBitFieldWrite16 (AcpiPmBaseAddress + 4, 10, 13, (UINT16) SuspendType);
+  IoOr16 (AcpiPmBaseAddress + 4, BIT13);
   CpuDeadLoop ();
 }
 
 /**
   Calling this function causes a system-wide reset. This sets
   all circuitry within the system to its initial state. This type of reset
   is asynchronous to system operation and operates without regard to
   cycle boundaries.
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 65b3df401abb..a5654a51183b 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -358,16 +358,18 @@  PciExBarInitialization (
 
 VOID
 MiscInitialization (
   VOID
   )
 {
   UINTN  PmCmd;
   UINTN  Pmba;
+  UINT32 PmbaAndVal;
+  UINT32 PmbaOrVal;
   UINTN  AcpiCtlReg;
   UINT8  AcpiEnBit;
 
   //
   // Disable A20 Mask
   //
   IoOr8 (0x92, BIT1);
 
@@ -380,22 +382,26 @@  MiscInitialization (
 
   //
   // Determine platform type and save Host Bridge DID to PCD
   //
   switch (mHostBridgeDevId) {
     case INTEL_82441_DEVICE_ID:
       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
+      PmbaOrVal  = PIIX4_PMBA_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
       break;
     case INTEL_Q35_MCH_DEVICE_ID:
       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
+      PmbaOrVal  = ICH9_PMBASE_VALUE;
       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
       break;
     default:
       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
         __FUNCTION__, mHostBridgeDevId));
       ASSERT (FALSE);
       return;
@@ -407,17 +413,17 @@  MiscInitialization (
   // has been configured (e.g., by Xen) and skip the setup here.
   // This matches the logic in AcpiTimerLibConstructor ().
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
     // 1. set PMBA
     //
-    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 
     //
     // 2. set PCICMD/IOSE
     //
     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 
     //
     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)