From patchwork Mon May 23 18:32:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 68410 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp237580qge; Mon, 23 May 2016 11:46:16 -0700 (PDT) X-Received: by 10.194.179.233 with SMTP id dj9mr263019wjc.115.1464029176749; Mon, 23 May 2016 11:46:16 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id fa10si45994322wjd.171.2016.05.23.11.46.16; Mon, 23 May 2016 11:46:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 204D8A75CA; Mon, 23 May 2016 20:46:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bd8XzEaoeXV3; Mon, 23 May 2016 20:46:04 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4D481A75CE; Mon, 23 May 2016 20:45:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C717BA7498 for ; Mon, 23 May 2016 20:32:27 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sVnSzQ-vn1ur for ; Mon, 23 May 2016 20:32:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 1CD42A74E9 for ; Mon, 23 May 2016 20:32:23 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u4NIWLMr024364; Mon, 23 May 2016 13:32:21 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4NIWLvi004427; Mon, 23 May 2016 13:32:21 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 23 May 2016 13:32:21 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4NIWLTw013450; Mon, 23 May 2016 13:32:21 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.83.68]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u4NIWL323228; Mon, 23 May 2016 13:32:21 -0500 (CDT) From: Suman Anna To: Tom Rini Date: Mon, 23 May 2016 13:32:17 -0500 Message-ID: <1464028337-13426-5-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1464028337-13426-1-git-send-email-s-anna@ti.com> References: <1464028337-13426-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 23 May 2016 20:45:41 +0200 Cc: u-boot@lists.denx.de, Keerthy Subject: [U-Boot] [PATCH 4/4] ARM: DRA7: Add macros for voltage values for all OPPs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna --- arch/arm/include/asm/arch-omap5/clock.h | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) -- 2.8.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 8c121d6..551c927 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -240,11 +240,21 @@ #define VDD_MM_ES2_LOW 880 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA7 1150 -#define VDD_CORE_DRA7 1150 -#define VDD_EVE_DRA7 1060 -#define VDD_GPU_DRA7 1060 -#define VDD_IVA_DRA7 1060 +#define VDD_MPU_DRA7_NOM 1150 +#define VDD_CORE_DRA7_NOM 1150 +#define VDD_EVE_DRA7_NOM 1060 +#define VDD_GPU_DRA7_NOM 1060 +#define VDD_IVA_DRA7_NOM 1060 + +/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ +#define VDD_EVE_DRA7_OD 1150 +#define VDD_GPU_DRA7_OD 1150 +#define VDD_IVA_DRA7_OD 1150 + +/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ +#define VDD_EVE_DRA7_HIGH 1250 +#define VDD_GPU_DRA7_HIGH 1250 +#define VDD_IVA_DRA7_HIGH 1250 /* Efuse register offsets for DRA7xx platform */ #define DRA752_EFUSE_BASE 0x4A002000 @@ -276,7 +286,14 @@ /* STD_FUSE_OPP_VMIN_MPU_4 */ #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) -/* Common Efuse register macros */ +/* Common voltage and Efuse register macros */ +/* DRA74x/DRA75x/DRA72x */ +#define VDD_MPU_DRA7 VDD_MPU_DRA7_NOM +#define VDD_CORE_DRA7 VDD_CORE_DRA7_NOM +#define VDD_EVE_DRA7 VDD_EVE_DRA7_NOM +#define VDD_GPU_DRA7 VDD_GPU_DRA7_NOM +#define VDD_IVA_DRA7 VDD_IVA_DRA7_NOM + #define STD_FUSE_OPP_VMIN_MPU STD_FUSE_OPP_VMIN_MPU_NOM #define STD_FUSE_OPP_VMIN_CORE STD_FUSE_OPP_VMIN_CORE_NOM #define STD_FUSE_OPP_VMIN_DSPEVE STD_FUSE_OPP_VMIN_DSPEVE_NOM