From patchwork Mon May 23 18:32:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 68411 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp237663qge; Mon, 23 May 2016 11:46:27 -0700 (PDT) X-Received: by 10.194.72.103 with SMTP id c7mr297953wjv.65.1464029187329; Mon, 23 May 2016 11:46:27 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id r203si17878429wmb.47.2016.05.23.11.46.27; Mon, 23 May 2016 11:46:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5090EA75D5; Mon, 23 May 2016 20:46:10 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NuhXr_y2M3nt; Mon, 23 May 2016 20:46:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9C87EA75F2; Mon, 23 May 2016 20:45:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D5A6CA74C5 for ; Mon, 23 May 2016 20:32:27 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZUiYRmcwbFN1 for ; Mon, 23 May 2016 20:32:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [198.47.19.12]) by theia.denx.de (Postfix) with ESMTPS id 17CA3A74A8 for ; Mon, 23 May 2016 20:32:23 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u4NIWL0r002200; Mon, 23 May 2016 13:32:21 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4NIWLBJ004418; Mon, 23 May 2016 13:32:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 23 May 2016 13:32:20 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4NIWK3a017349; Mon, 23 May 2016 13:32:20 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.83.68]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u4NIWK323216; Mon, 23 May 2016 13:32:20 -0500 (CDT) From: Suman Anna To: Tom Rini Date: Mon, 23 May 2016 13:32:14 -0500 Message-ID: <1464028337-13426-2-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.8.2 In-Reply-To: <1464028337-13426-1-git-send-email-s-anna@ti.com> References: <1464028337-13426-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 23 May 2016 20:45:41 +0200 Cc: u-boot@lists.denx.de, Keerthy Subject: [U-Boot] [PATCH 1/4] ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The current OPP_NOM voltage values defined for the MPU and CORE voltage domains are based on the initial DRA75x_74x_SR1.1_DM data manual. As per this DM, the PMIC boot voltage can be set to either 1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE. While the current values are correct, the latter set of values are the values that are common across all DRA75x, DRA72x SoCs and for all current Silicon revisions. So, update both the MPU and CORE OPP_NOM voltages to 1.15V. The macros are also slightly reorganized so that both the MPU and CORE voltage domain values are defined together. Signed-off-by: Suman Anna --- arch/arm/include/asm/arch-omap5/clock.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.8.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 38d50d6..9180c67 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -240,17 +240,17 @@ #define VDD_MM_ES2_LOW 880 /* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA752 1100 +#define VDD_MPU_DRA752 1150 +#define VDD_CORE_DRA752 1150 #define VDD_EVE_DRA752 1060 #define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1060 #define VDD_IVA_DRA752 1060 /* DRA72x voltage settings in mv for OPP_NOM per DM */ -#define VDD_MPU_DRA72x 1100 +#define VDD_MPU_DRA72x 1150 +#define VDD_CORE_DRA72x 1150 #define VDD_EVE_DRA72x 1060 #define VDD_GPU_DRA72x 1060 -#define VDD_CORE_DRA72x 1060 #define VDD_IVA_DRA72x 1060 /* Efuse register offsets for DRA7xx platform */