From patchwork Tue Feb 21 06:19:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Daniel Kachhap X-Patchwork-Id: 6851 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 64DBF23EB0 for ; Tue, 21 Feb 2012 06:21:48 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 25E7AA185A5 for ; Tue, 21 Feb 2012 06:21:48 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id z7so11912584iab.11 for ; Mon, 20 Feb 2012 22:21:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:x-forwarded-to:x-forwarded-for:delivered-to :received-spf:dkim-signature:sender:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=p2cK145yIK2zHFvLaQJwZqJIkYmthys7yCSYZLbI59U=; b=nH1o7HfdD3FU3wVVzUWlKR9tgIEa7GFDDKAiTy0PQPd4oa8fRVzitc2McLS4H/us4v Cm5FfdAYL9vs2ErL+Vc2p1tP/jy3ThilAvX7Emluo3Pz4rafXE7QpgDFtlrWqH3tUmFS RqRlhO26jHTdP3kIOyRDUUYFdgQNPxhzzYQvs= MIME-Version: 1.0 Received: by 10.50.89.196 with SMTP id bq4mr14065899igb.26.1329805307950; Mon, 20 Feb 2012 22:21:47 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10csp80753ibr; Mon, 20 Feb 2012 22:21:47 -0800 (PST) Received: by 10.68.132.106 with SMTP id ot10mr29918097pbb.74.1329805306945; Mon, 20 Feb 2012 22:21:46 -0800 (PST) Received: from mail-pw0-f50.google.com (mail-pw0-f50.google.com [209.85.160.50]) by mx.google.com with ESMTPS id f3si31577980pbp.7.2012.02.20.22.21.46 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:46 -0800 (PST) Received-SPF: pass (google.com: domain of amitdanielk@gmail.com designates 209.85.160.50 as permitted sender) client-ip=209.85.160.50; Authentication-Results: mx.google.com; spf=pass (google.com: domain of amitdanielk@gmail.com designates 209.85.160.50 as permitted sender) smtp.mail=amitdanielk@gmail.com; dkim=pass header.i=@gmail.com Received: by mail-pw0-f50.google.com with SMTP id wy7so7968814pbc.37 for ; Mon, 20 Feb 2012 22:21:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=p2cK145yIK2zHFvLaQJwZqJIkYmthys7yCSYZLbI59U=; b=jX1BC79wxSHbDT7LJ0vCvJsZGfUtUnbnUHGO8JQ8OGRRhgbs3PjMirdrb2O7tYQRaP Rt7hM3TohYfdhul7h3kvgBPa3tfHz2fJtxgpTGT1zzjZxnoT9ssiMg/S1tbdv8N1ndTC I4y5VxOoAFeWaxAOfdWtctdo0tIUYld8PfKJg= Received: by 10.68.202.40 with SMTP id kf8mr52937673pbc.153.1329805305971; Mon, 20 Feb 2012 22:21:45 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id vy2sm7541182pbb.48.2012.02.20.22.21.43 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Feb 2012 22:21:45 -0800 (PST) Sender: amit kachhap From: Amit Daniel Kachhap To: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, amit.kachhap@linaro.org, patches@linaro.org Subject: [PATCH V6 2/5] ARM: s5p: add L2 early resume code Date: Tue, 21 Feb 2012 11:49:47 +0530 Message-Id: <1329805190-8874-3-git-send-email-amit.kachhap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> References: <1329805190-8874-1-git-send-email-amit.kachhap@linaro.org> X-Gm-Message-State: ALoCoQmV8LN8LawtSbWNZBpQDhpgGShbP7103HGGKdVuCM/zmG4iwL+D0sVmCKJ1jldGzna5Fuic This patch adds code to resume L2 before MMU is enabled in suspend and cpuidle resume paths. s3c_cpu_resume is moved to the data section with appropriate comments. Signed-off-by: Lorenzo Pieralisi Signed-off-by: Amit Daniel Kachhap --- arch/arm/plat-s5p/sleep.S | 44 ++++++++++++++++++++++++++++++++++++++------ 1 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S index 0fd591b..006bd01 100644 --- a/arch/arm/plat-s5p/sleep.S +++ b/arch/arm/plat-s5p/sleep.S @@ -23,9 +23,18 @@ */ #include -#include +#include +#include - .text +/* + * The following code is located into the .data section. This is to + * allow l2x0_regs_phys to be accessed with a relative load while we + * can't rely on any MMU translation. We could have put l2x0_regs_phys + * in the .text section as well, but some setups might insist on it to + * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) + */ + .data + .align /* * sleep magic, to allow the bootloader to check for an valid @@ -39,11 +48,34 @@ * s3c_cpu_resume * * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) */ ENTRY(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + adr r0, l2x0_regs_phys + ldr r0, [r0] + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne resume_l2on + ldr r2, [r0, #L2X0_R_AUX_CTRL] + str r2, [r1, #L2X0_AUX_CTRL] + ldr r2, [r0, #L2X0_R_TAG_LATENCY] + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] + str r2, [r1, #L2X0_PREFETCH_CTRL] + ldr r2, [r0, #L2X0_R_PWR_CTRL] + str r2, [r1, #L2X0_POWER_CTRL] + mov r2, #1 + str r2, [r1, #L2X0_CTRL] +resume_l2on: +#endif b cpu_resume +ENDPROC(s3c_cpu_resume) +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0 +#endif