| Message ID | 20230607103459.1222426-1-robert.hodaszi@digi.com |
|---|---|
| State | New |
| Headers | show |
| Series | Revert "tty: serial: fsl_lpuart: Fix the wrong RXWATER setting for rx dma case" | expand |
On 2023. 06. 08. 4:20, Sherry Sun wrote: > Hi Robert, > I understand your concern, fortunately, LPUART IP provides the Receiver Idle Empty function, which can avoid the receive data being trapped in the RX FIFO. For more details you can check my patch below. > Hi, Although I can see RXIDEN in the i.MX8 RM, it's not in LS1028A's LPUART FIFO register. Seems not all LPUART IPs have this. Best regards, Robert
On 2023. 06. 08. 11:58, Sherry Sun wrote: > Oh, maybe LS1028 use the old IP version LPUART. > If this is the case, I suggest that you can set the rx_watermark of ls1028 to 0. > > static const struct lpuart_soc_data ls1028a_data = { > .devtype = LS1028A_LPUART, > .iotype = UPIO_MEM32, > .rx_watermark = 0, > }; > > Best Regards > Sherry Ok, that should work in my case, as that's basically the same as reverting the patch. And I'm not losing anything on non-DMA case, as DMA is always used. But the other platforms should be fixed as well, as it is a global issue across platforms using DMA with LPUART. So please push up then your previous patch with RXIDEN for platforms supporting that. Thanks, Robert
On 2023. 06. 08. 12:45, Sherry Sun wrote: > Yes, the RXIDEN patch has already been upstreamed, you can check the latest kernel. > > Best Regards > Sherry Ahh, sorry, you're right! I'm using 6.3, and it's there. I forgot to check. OK, then I'll push up another patch with setting the rx_watermark = 0 for LS1028A. Thanks, Robert
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 7486a2b8556c..8f1bb0a378d4 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1762,6 +1762,12 @@ static void lpuart32_configure(struct lpuart_port *sport) { unsigned long temp; + if (sport->lpuart_dma_rx_use) { + /* RXWATER must be 0 */ + temp = lpuart32_read(&sport->port, UARTWATER); + temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); + lpuart32_write(&sport->port, temp, UARTWATER); + } temp = lpuart32_read(&sport->port, UARTCTRL); if (!sport->lpuart_dma_rx_use) temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
This reverts commit 9ad9df8447547febe9dd09b040f4528a09e495f0. LSUART's datasheet incorrectly states that RXWATER must be greater than 0. Having that set to 1 is causing a one character delay on the receive path. Signed-off-by: Robert Hodaszi <robert.hodaszi@digi.com> --- drivers/tty/serial/fsl_lpuart.c | 6 ++++++ 1 file changed, 6 insertions(+)