From patchwork Mon Jun 6 15:59:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 69422 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp1551581qgf; Mon, 6 Jun 2016 08:59:44 -0700 (PDT) X-Received: by 10.107.202.5 with SMTP id a5mr21846892iog.38.1465228783457; Mon, 06 Jun 2016 08:59:43 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ke8si27279031pad.150.2016.06.06.08.59.43; Mon, 06 Jun 2016 08:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753074AbcFFP7l (ORCPT + 7 others); Mon, 6 Jun 2016 11:59:41 -0400 Received: from foss.arm.com ([217.140.101.70]:37467 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753065AbcFFP7k (ORCPT ); Mon, 6 Jun 2016 11:59:40 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9EDFB43A; Mon, 6 Jun 2016 09:00:13 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.207.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A9D393F253; Mon, 6 Jun 2016 08:59:38 -0700 (PDT) From: Sudeep Holla To: linux-arm-kernel@lists.infradead.org Cc: Sudeep Holla , Jon Medhurst , Mathieu Poirier , Suzuki K Poulose , Liviu Dudau , Lorenzo Pieralisi , devicetree@vger.kernel.org Subject: [PATCH 2/3] arm64: dts: juno: add arm,primecell-periphid override Date: Mon, 6 Jun 2016 16:59:24 +0100 Message-Id: <1465228765-14038-3-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1465228765-14038-1-git-send-email-sudeep.holla@arm.com> References: <1465228765-14038-1-git-send-email-sudeep.holla@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Linux AMBA framework probes the peripheral ids when adding the amba devices very early on the boot. Generally they are on APB bus and just require APB clocks to be on even when most of the core logic of the IP is powered down. However on Juno, the entire debugsys domain needs to be ON to access those CID/PID registers and hence broken by design. Accessing those while debugsys power domain is off will lead to the bridge stalling the transactions instead of returning the slave error. Since keeping the power domain on by default affects the core power(by preventing cores entering deeper idle states), it's not feasible solution. Instead we can provide arm,primecell-periphid override in the device tree that prevents accessing the device early in the boot. However the power domains can be enabled whenever required using runtime PM and associated power domains. Cc: Liviu Dudau Cc: Lorenzo Pieralisi Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++ arch/arm64/boot/dts/arm/juno-r2.dts | 6 ++++++ arch/arm64/boot/dts/arm/juno.dts | 6 ++++++ 4 files changed, 31 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Liviu Dudau diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 90a8710f7032..49fa55cdc977 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -63,6 +63,14 @@ */ etf@20010000 { compatible = "arm,coresight-tmc", "arm,primecell"; + /* + * The primecell peripheral id is explicitly specified here with + * the actual hardware value. It's not any override. It's + * required to workaround an errata to avoid bus stalls early + * in the boot when AMBA primecell ids are probed before the + * actual power domain can be enabled using SCPI. + */ + arm,primecell-periphid = <0x001bb961>; reg = <0 0x20010000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -92,6 +100,7 @@ tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; + arm,primecell-periphid = <0x004bb912>; reg = <0 0x20030000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -106,6 +115,7 @@ main_funnel@20040000 { compatible = "arm,coresight-funnel", "arm,primecell"; + arm,primecell-periphid = <0x002bb908>; reg = <0 0x20040000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -142,6 +152,7 @@ etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; reg = <0 0x20070000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -192,6 +203,7 @@ cluster0_funnel@220c0000 { compatible = "arm,coresight-funnel", "arm,primecell"; + arm,primecell-periphid = <0x002bb908>; reg = <0 0x220c0000 0 0x1000>; clocks = <&soc_smc50mhz>; @@ -227,6 +239,7 @@ cluster1_funnel@230c0000 { compatible = "arm,coresight-funnel", "arm,primecell"; + arm,primecell-periphid = <0x002bb908>; reg = <0 0x230c0000 0 0x1000>; clocks = <&soc_smc50mhz>; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index f4f8f54f8b85..c3c9fdff49bf 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -184,24 +184,30 @@ &etm0 { cpu = <&A57_0>; + arm,primecell-periphid = <0x002bb95e>; }; &etm1 { cpu = <&A57_1>; + arm,primecell-periphid = <0x002bb95e>; }; &etm2 { cpu = <&A53_0>; + arm,primecell-periphid = <0x003bb95d>; }; &etm3 { cpu = <&A53_1>; + arm,primecell-periphid = <0x003bb95d>; }; &etm4 { cpu = <&A53_2>; + arm,primecell-periphid = <0x003bb95d>; }; &etm5 { cpu = <&A53_3>; + arm,primecell-periphid = <0x003bb95d>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index d903e545b64c..c672c978f89d 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -184,24 +184,30 @@ &etm0 { cpu = <&A72_0>; + arm,primecell-periphid = <0x000bb95a>; }; &etm1 { cpu = <&A72_1>; + arm,primecell-periphid = <0x000bb95a>; }; &etm2 { cpu = <&A53_0>; + arm,primecell-periphid = <0x003bb95d>; }; &etm3 { cpu = <&A53_1>; + arm,primecell-periphid = <0x003bb95d>; }; &etm4 { cpu = <&A53_2>; + arm,primecell-periphid = <0x003bb95d>; }; &etm5 { cpu = <&A53_3>; + arm,primecell-periphid = <0x003bb95d>; }; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index a7270eff6939..0528e47e66d1 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -176,24 +176,30 @@ &etm0 { cpu = <&A57_0>; + arm,primecell-periphid = <0x000bb95e>; }; &etm1 { cpu = <&A57_1>; + arm,primecell-periphid = <0x000bb95e>; }; &etm2 { cpu = <&A53_0>; + arm,primecell-periphid = <0x000bb95d>; }; &etm3 { cpu = <&A53_1>; + arm,primecell-periphid = <0x000bb95d>; }; &etm4 { cpu = <&A53_2>; + arm,primecell-periphid = <0x000bb95d>; }; &etm5 { cpu = <&A53_3>; + arm,primecell-periphid = <0x000bb95d>; };