diff mbox series

[RFC] ASoC: fsl_sai: Do not set MCTL_MCLK_EN based on the number of registers

Message ID 20230706131829.1862750-1-festevam@gmail.com
State New
Headers show
Series [RFC] ASoC: fsl_sai: Do not set MCTL_MCLK_EN based on the number of registers | expand

Commit Message

Fabio Estevam July 6, 2023, 1:18 p.m. UTC 
From: Fabio Estevam <festevam@denx.de>

Since commit ff87d619ac18 ("ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for
master mode") Andreas reports that on an i.MX8MP-based system where
MCLK needs to be an input, the MCLK pin is actually an output, despite
not having the 'fsl,sai-mclk-direction-output' property present in the
devicetree.

This commit explains the following:

"On i.MX8MM, the MCTL_MCLK_EN bit it is not only the gate
for MCLK output to PAD, but also the gate bit between
root clock and SAI module, So it is need to be enabled
for master mode, otherwise there is no bclk generated."

Currently, the decision of using MCTL_MCLK_EN as a clock gate is based
on the number of SAI registers present on a platform.

This is fragile as it causes issues on i.MX8MP, for example.

Fix the problem by introducing a new boolean mclk_en_gates_clock member in
the fsl_sai_soc_data structure that indicates that the MCTL_MCLK_EN bit
also acts as a gate between the root clock and the SAI block.

This allows i.MX8MM to turn on FSL_SAI_MCTL_MCLK_EN as intended and other
SoCs such as i.MX8MP can still use MCLK as input.

Fixes: ff87d619ac18 ("ASoC: fsl_sai: Enable MCTL_MCLK_EN bit for master mode")
Reported-by: Andreas Henriksson <andreas@fatal.se>
Signed-off-by: Fabio Estevam <festevam@denx.de>

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Hi Shengjiu,

Is imx8mm the only SoC that needs mclk_en_gates_clock = true?

What about imx8mn and imx93?

 sound/soc/fsl/fsl_sai.c | 12 +++++++++++-
 sound/soc/fsl/fsl_sai.h |  1 +
 2 files changed, 12 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 5e09f634c61b..e4dc6964f011 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -507,7 +507,7 @@  static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 				   savediv / 2 - 1);
 	}
 
-	if (sai->soc_data->max_register >= FSL_SAI_MCTL) {
+	if (sai->soc_data->mclk_en_gates_clock) {
 		/* SAI is in master mode at this point, so enable MCLK */
 		regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
 				   FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
@@ -1513,6 +1513,7 @@  static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
 	.reg_offset = 0,
 	.mclk0_is_mclk1 = false,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RMR,
 };
 
@@ -1524,6 +1525,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
 	.reg_offset = 0,
 	.mclk0_is_mclk1 = true,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RMR,
 };
 
@@ -1535,6 +1537,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
 	.reg_offset = 8,
 	.mclk0_is_mclk1 = false,
 	.flags = PMQOS_CPU_LATENCY,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RMR,
 };
 
@@ -1546,6 +1549,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
 	.reg_offset = 8,
 	.mclk0_is_mclk1 = false,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RMR,
 };
 
@@ -1557,6 +1561,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
 	.reg_offset = 0,
 	.mclk0_is_mclk1 = false,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RMR,
 };
 
@@ -1568,6 +1573,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = {
 	.mclk0_is_mclk1 = false,
 	.pins = 8,
 	.flags = 0,
+	.mclk_en_gates_clock = true,
 	.max_register = FSL_SAI_MCTL,
 };
 
@@ -1579,6 +1585,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8mn_data = {
 	.mclk0_is_mclk1 = false,
 	.pins = 8,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_MDIV,
 };
 
@@ -1590,6 +1597,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = {
 	.mclk0_is_mclk1 = false,
 	.pins = 8,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_MDIV,
 	.mclk_with_tere = true,
 };
@@ -1602,6 +1610,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = {
 	.mclk0_is_mclk1 = false,
 	.pins = 4,
 	.flags = PMQOS_CPU_LATENCY,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_RTCAP,
 };
 
@@ -1613,6 +1622,7 @@  static const struct fsl_sai_soc_data fsl_sai_imx93_data = {
 	.mclk0_is_mclk1 = false,
 	.pins = 4,
 	.flags = 0,
+	.mclk_en_gates_clock = false,
 	.max_register = FSL_SAI_MCTL,
 	.max_burst = {8, 8},
 };
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 8254c3547b87..473260b0fbea 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -232,6 +232,7 @@  struct fsl_sai_soc_data {
 	bool use_edma;
 	bool mclk0_is_mclk1;
 	bool mclk_with_tere;
+	bool mclk_en_gates_clock;
 	unsigned int fifo_depth;
 	unsigned int pins;
 	unsigned int reg_offset;