From patchwork Wed Feb 29 14:14:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 7003 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3B23323E01 for ; Wed, 29 Feb 2012 14:14:48 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id D0056A1813A for ; Wed, 29 Feb 2012 14:14:47 +0000 (UTC) Received: by iage36 with SMTP id e36so3329945iag.11 for ; Wed, 29 Feb 2012 06:14:47 -0800 (PST) Received: from mr.google.com ([10.43.52.74]) by 10.43.52.74 with SMTP id vl10mr288563icb.55.1330524887340 (num_hops = 1); Wed, 29 Feb 2012 06:14:47 -0800 (PST) Received: by 10.43.52.74 with SMTP id vl10mr240804icb.55.1330524887244; Wed, 29 Feb 2012 06:14:47 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp3811ibg; Wed, 29 Feb 2012 06:14:46 -0800 (PST) Received: by 10.68.243.197 with SMTP id xa5mr6310354pbc.68.1330524886243; Wed, 29 Feb 2012 06:14:46 -0800 (PST) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id o6si26501083pba.288.2012.02.29.06.14.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 06:14:46 -0800 (PST) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1S2kIm-0001Et-RZ from Andrew_Stubbs@mentor.com ; Wed, 29 Feb 2012 06:14:44 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 29 Feb 2012 06:14:44 -0800 Received: from [172.30.13.193] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Wed, 29 Feb 2012 14:14:42 +0000 Message-ID: <4F4E32CF.1040405@codesourcery.com> Date: Wed, 29 Feb 2012 14:14:39 +0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: "patches@linaro.org" Subject: Re: [PATCH][ARM] NEON DImode neg References: <4F4D12C5.9070805@codesourcery.com> In-Reply-To: <4F4D12C5.9070805@codesourcery.com> X-OriginalArrivalTime: 29 Feb 2012 14:14:44.0420 (UTC) FILETIME=[7C403840:01CCF6EC] X-Gm-Message-State: ALoCoQmffyQqVJmMIqFUCCZ1CV+c3Cm3qbLxRkjC1GSwXx3488gsKfYq2JjoJXkMXbWxdwlzayU7 On 28/02/12 17:45, Andrew Stubbs wrote: > This patch adds a DImode negate pattern for NEON. Oops, that patch completely failed to allow for the fallback to instructions that work in core registers. It also forgot to mention that the CC register was clobbered. This patch is the same except that it addresses those deficiencies. The outputs are the same. Ok for 4.8? Andrew 2012-02-29 Andrew Stubbs gcc/ * config/arm/arm.md (negdi2): Use gen_negdi2_neon. * config/arm/neon.md (negdi2_neon): New insn. Also add splitters for core and NEON registers. --- gcc/config/arm/arm.md | 8 +++++++- gcc/config/arm/neon.md | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 751997f..f1dbbf7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4048,7 +4048,13 @@ (neg:DI (match_operand:DI 1 "s_register_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" - "" + { + if (TARGET_NEON) + { + emit_insn (gen_negdi2_neon (operands[0], operands[1])); + DONE; + } + } ) ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index d7caa37..b040ab1 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -922,6 +922,43 @@ (const_string "neon_int_3")))] ) +(define_insn "negdi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?r,?&r,?w") + (neg:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w"))) + (clobber (match_scratch:DI 2 "=w, X, X, w")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "arch" "nota8,*,*,onlya8")] +) + +; Split negdi2_neon for vfp registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" + [(set (match_dup 2) (const_int 0)) + (parallel [(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + +; Split negdi2_neon for core registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && reload_completed + && arm_general_register_operand (operands[0], DImode)" + [(parallel [(set (match_dup 0) (neg:DI (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + (define_insn "*umin3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")