From patchwork Mon Mar 21 17:29:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 704 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:44:57 -0000 Delivered-To: patches@linaro.org Received: by 10.220.28.198 with SMTP id n6cs144586vcc; Mon, 21 Mar 2011 10:29:38 -0700 (PDT) Received: by 10.14.9.231 with SMTP id 79mr1412072eet.241.1300728576798; Mon, 21 Mar 2011 10:29:36 -0700 (PDT) Received: from mtagate7.uk.ibm.com (mtagate7.uk.ibm.com [194.196.100.167]) by mx.google.com with ESMTPS id t3si6527473eeh.31.2011.03.21.10.29.36 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 21 Mar 2011 10:29:36 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning uweigand@de.ibm.com does not designate 194.196.100.167 as permitted sender) client-ip=194.196.100.167; Authentication-Results: mx.google.com; spf=softfail (google.com: domain of transitioning uweigand@de.ibm.com does not designate 194.196.100.167 as permitted sender) smtp.mail=uweigand@de.ibm.com Received: from d06nrmr1507.portsmouth.uk.ibm.com (d06nrmr1507.portsmouth.uk.ibm.com [9.149.38.233]) by mtagate7.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p2LHTaad000923 for ; Mon, 21 Mar 2011 17:29:36 GMT Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1507.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p2LHU1r91937608 for ; Mon, 21 Mar 2011 17:30:01 GMT Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p2LHTZTX024482 for ; Mon, 21 Mar 2011 11:29:35 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id p2LHTYe9024479; Mon, 21 Mar 2011 11:29:34 -0600 Message-Id: <201103211729.p2LHTYe9024479@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Mon, 21 Mar 2011 18:29:34 +0100 Subject: [commit, arm] Fix minor ARM prologue parsing bug To: gdb-patches@sourceware.org Date: Mon, 21 Mar 2011 18:29:34 +0100 (CET) From: "Ulrich Weigand" Cc: patches@linaro.org X-Mailer: ELM [version 2.5 PL2] MIME-Version: 1.0 Hello, this patch fixes a minor problem in ARM prologue parsing: we're usually careful to skip over all non-prologue instructions; however, there is one weird case where prologue parsing is completely aborted instead, namely when encountering a load or load multiple instruction via some register other than the stack pointer. This doesn't really make sense, and causes backtrace failures with certain glibc build. The patch below fixes this by treating such load instruction just like any other non-prologue instruction. Tested on armv7l-linux-gnueabi with no regressions. Committed to mainline. Bye, Ulrich ChangeLog: * arm-tdep.c (arm_analyze_prologue): Do not abort parsing when encountering a load via a non-SP register. Index: gdb/arm-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/arm-tdep.c,v retrieving revision 1.335 diff -u -p -r1.335 arm-tdep.c --- gdb/arm-tdep.c 11 Mar 2011 14:48:55 -0000 1.335 +++ gdb/arm-tdep.c 18 Mar 2011 22:05:25 -0000 @@ -1856,23 +1856,15 @@ arm_analyze_prologue (struct gdbarch *gd else if (arm_instruction_changes_pc (insn)) /* Don't scan past anything that might change control flow. */ break; - else if ((insn & 0xfe500000) == 0xe8100000) /* ldm */ - { - /* Ignore block loads from the stack, potentially copying - parameters from memory. */ - if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) - continue; - else - break; - } - else if ((insn & 0xfc500000) == 0xe4100000) - { - /* Similarly ignore single loads from the stack. */ - if (pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) - continue; - else - break; - } + else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ + && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) + /* Ignore block loads from the stack, potentially copying + parameters from memory. */ + continue; + else if ((insn & 0xfc500000) == 0xe4100000 + && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) + /* Similarly ignore single loads from the stack. */ + continue; else if ((insn & 0xffff0ff0) == 0xe1a00000) /* MOV Rd, Rm. Skip register copies, i.e. saves to another register instead of the stack. */