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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id g71si194729pfj.152.2016.06.22.07.32.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Jun 2016 07:32:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 075A91A1E08; Wed, 22 Jun 2016 07:32:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 68EB91A1E04 for ; Wed, 22 Jun 2016 07:32:51 -0700 (PDT) Received: by mail-wm0-x234.google.com with SMTP id r201so8931673wme.1 for ; Wed, 22 Jun 2016 07:32:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=u8tEJsoYghI7TGbXBwOeIQ959K+cdY4yPwqY49XpxKA=; b=FlWTNCQoPMPZeJBTTWNYvVrFImGb3dOO7BGqMQhkzBvZ9tK67OEYP3h5Y3qOARAw29 nnE3ZbSGcwkbE5gMWlwC1ZzcUcMn+JjBEu4fA6GQYKRXcp7cnDiq/D/PP5yW+pJtvQ0h nK5Yrfi2p9EW+ZsHwO0+KpwVOefMmOEPk+MGE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=u8tEJsoYghI7TGbXBwOeIQ959K+cdY4yPwqY49XpxKA=; b=JvYe5xlUCnGsNMvAF3vA8SMEHGha+X323o2ENl5rUv8iY50OD8AZz0jU1Z/2e96ndp g0ZelgdSYVwbgHNuVt2WJP389USGtRlPRbQpIB4IWe29EV62Fq0iZuBbd4e2wTrK5Mqo UTy32VRkYBqqjU5V3fT5WTUG286OhkMzvtmDH01IRce5DGx3hQSSdN/A8MFmkkRjrGcY Gl6jzAgGBll5o9EX0ce4Ltmfm+BFN5Pig7l7CnJZSKDIpmNIw5rmAiR0A96oq4Xy64o6 jBl1KfjnyD58+h34mr9mx/q63OkhOYQsvYId3UULsxYB6xLepZkD1s503XkOEKhiGXIV PcQg== X-Gm-Message-State: ALyK8tK0OckVvGPd52QBBhE+qX5sJtuuoiw5Nt8IiPgaOBRfWqInLRi9LhiG1Jv+4GiK7CqB X-Received: by 10.194.113.136 with SMTP id iy8mr25251270wjb.174.1466605939141; Wed, 22 Jun 2016 07:32:19 -0700 (PDT) Received: from localhost.localdomain ([188.203.148.129]) by smtp.gmail.com with ESMTPSA id q203sm896753wmd.24.2016.06.22.07.32.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jun 2016 07:32:18 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 22 Jun 2016 16:32:15 +0200 Message-Id: <1466605935-19217-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [edk2] [PATCH] ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, Ard Biesheuvel , shlomo.pongratz@huawei.com, shlomopongratz@gmail.com, p.fedin@samsung.com, leif.lindholm@linaro.org, shannon.zhao@linaro.org, lersek@redhat.com, christoffer.dall@linaro.org MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- This is the EDK2 counterpart of Peter's patch against the Linux kernel 7c9b973061b0 ("irqchip/gic-v3: Configure all interrupts as non-secure Group-1") which tweaks the GICv3 driver so that it works with the GICv3 emulation in QEMU, which only emulates a single GIC security state when running without the security extensions. ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 16 ++++++++++++++++ ArmPkg/Include/Library/ArmGicLib.h | 5 +++-- 2 files changed, 19 insertions(+), 2 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Tested-by: Drew Jones Reviewed-by: Leif Lindholm diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 50fa56262eaf..106c669fcb87 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -297,6 +297,22 @@ GicV3DxeInitialize ( MpId = ArmReadMpidr (); CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3); + if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) { + // + // If the Disable Security (DS) control bit is set, we are dealing with a + // GIC that has only one security state. In this case, let's assume we are + // executing in non-secure state (which is appropriate for DXE modules) + // and that no other firmware has performed any configuration on the GIC. + // This means we need to reconfigure all interrupts to non-secure Group 1 + // first. + // + MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff); + + for (Index = 32; Index < mGicNumInterrupts; Index += 32) { + MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff); + } + } + // Route the SPIs to the primary CPU. SPIs start at the INTID 32 for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM); diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index 10c4a9d72eb2..4364f3ffef46 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -47,8 +47,9 @@ // GICv3 specific registers #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers -// the Affinity Routing Enable (ARE) bit in GICD_CTLR -#define ARM_GIC_ICDDCR_ARE (1 << 4) +// GICD_CTLR bits +#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) +#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) // // GIC Redistributor