| Message ID | bf912d5f5e74b43903a84262565f564bfe0fed7e.1691047370.git.michal.simek@amd.com |
|---|---|
| State | Accepted |
| Commit | 92b5b53380955e6ca3c5786c72dbc99dcdfa8e4f |
| Headers | show
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From: Michal Simek <michal.simek@amd.com>
To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>,
<michal.simek@xilinx.com>, <git@xilinx.com>
CC: Adrian Hunter <adrian.hunter@intel.com>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
<devicetree@vger.kernel.org>, <linux-mmc@vger.kernel.org>
Subject: [PATCH] dt-bindings: mmc: arasan,sdci: Add power-domains and iommus
properties
Date: Thu, 3 Aug 2023 09:22:56 +0200
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| Series |
dt-bindings: mmc: arasan,sdci: Add power-domains and iommus properties
|
expand
|
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index a6c19a6cc99e..3e99801f77d2 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -160,6 +160,12 @@ properties: description: The MIO bank number in which the command and data lines are configured. + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + dependencies: '#clock-cells': [ clock-output-names ]
ZynqMP SDHCI Arasan IP core has own power domain and also iommu ID that's why describe optional power-domains and iommus properties. Signed-off-by: Michal Simek <michal.simek@amd.com> --- Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 6 ++++++ 1 file changed, 6 insertions(+)