| Message ID | 20230808082738.122804-11-krzysztof.kozlowski@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | clk: samsung: remove number of clocks from bindings | expand |
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Tuesday, August 8, 2023 1:58 PM > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester > Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa > <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim > Akhtar <alim.akhtar@samsung.com>; Michael Turquette > <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob > Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; > linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org > Subject: [PATCH 10/11] clk: samsung: exynoautov9: do not define number of > clocks in bindings > > Number of clocks supported by Linux drivers might vary - sometimes we add > new clocks, not exposed previously. Therefore this number of clocks should > not be in the bindings, because otherwise we should not change it. > > Define number of clocks per each clock controller inside the driver directly. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 9 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynosautov9.c > b/drivers/clk/samsung/clk-exynosautov9.c > index ddef546be545..e9c06eb93e66 100644 > --- a/drivers/clk/samsung/clk-exynosautov9.c > +++ b/drivers/clk/samsung/clk-exynosautov9.c > @@ -16,6 +16,17 @@ > #include "clk.h" > #include "clk-exynos-arm64.h" > > +/* NOTE: Must be equal to the last clock ID increased by one */ > +#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS > + 1) > +#define CLKS_NR_BUSMC > (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) > +#define CLKS_NR_CORE > (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) > +#define CLKS_NR_FSYS0 > (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) > +#define CLKS_NR_FSYS1 > (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) > +#define CLKS_NR_FSYS2 > (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) > +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 > + 1) > +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 > + 1) > +#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 > + 1) > + > /* ---- CMU_TOP ------------------------------------------------------------ */ > > /* Register Offset definitions for CMU_TOP (0x1b240000) */ @@ -941,7 > +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst > = { > .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), > .gate_clks = top_gate_clks, > .nr_gate_clks = ARRAY_SIZE(top_gate_clks), > - .nr_clk_ids = TOP_NR_CLK, > + .nr_clk_ids = CLKS_NR_TOP, > .clk_regs = top_clk_regs, > .nr_clk_regs = ARRAY_SIZE(top_clk_regs), > }; > @@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info > busmc_cmu_info __initconst = { > .nr_div_clks = ARRAY_SIZE(busmc_div_clks), > .gate_clks = busmc_gate_clks, > .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks), > - .nr_clk_ids = BUSMC_NR_CLK, > + .nr_clk_ids = CLKS_NR_BUSMC, > .clk_regs = busmc_clk_regs, > .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs), > .clk_name = "dout_clkcmu_busmc_bus", > @@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info > core_cmu_info __initconst = { > .nr_div_clks = ARRAY_SIZE(core_div_clks), > .gate_clks = core_gate_clks, > .nr_gate_clks = ARRAY_SIZE(core_gate_clks), > - .nr_clk_ids = CORE_NR_CLK, > + .nr_clk_ids = CLKS_NR_CORE, > .clk_regs = core_clk_regs, > .nr_clk_regs = ARRAY_SIZE(core_clk_regs), > .clk_name = "dout_clkcmu_core_bus", > @@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info > fsys0_cmu_info __initconst = { > .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), > .gate_clks = fsys0_gate_clks, > .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), > - .nr_clk_ids = FSYS0_NR_CLK, > + .nr_clk_ids = CLKS_NR_FSYS0, > .clk_regs = fsys0_clk_regs, > .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), > .clk_name = "dout_clkcmu_fsys0_bus", > @@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info > fsys1_cmu_info __initconst = { > .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), > .gate_clks = fsys1_gate_clks, > .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), > - .nr_clk_ids = FSYS1_NR_CLK, > + .nr_clk_ids = CLKS_NR_FSYS1, > .clk_regs = fsys1_clk_regs, > .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), > .clk_name = "dout_clkcmu_fsys1_bus", > @@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info > fsys2_cmu_info __initconst = { > .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), > .gate_clks = fsys2_gate_clks, > .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), > - .nr_clk_ids = FSYS2_NR_CLK, > + .nr_clk_ids = CLKS_NR_FSYS2, > .clk_regs = fsys2_clk_regs, > .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), > .clk_name = "dout_clkcmu_fsys2_bus", > @@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info > peric0_cmu_info __initconst = { > .nr_div_clks = ARRAY_SIZE(peric0_div_clks), > .gate_clks = peric0_gate_clks, > .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), > - .nr_clk_ids = PERIC0_NR_CLK, > + .nr_clk_ids = CLKS_NR_PERIC0, > .clk_regs = peric0_clk_regs, > .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), > .clk_name = "dout_clkcmu_peric0_bus", > @@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info > peric1_cmu_info __initconst = { > .nr_div_clks = ARRAY_SIZE(peric1_div_clks), > .gate_clks = peric1_gate_clks, > .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), > - .nr_clk_ids = PERIC1_NR_CLK, > + .nr_clk_ids = CLKS_NR_PERIC1, > .clk_regs = peric1_clk_regs, > .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), > .clk_name = "dout_clkcmu_peric1_bus", > @@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info > peris_cmu_info __initconst = { > .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), > .gate_clks = peris_gate_clks, > .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), > - .nr_clk_ids = PERIS_NR_CLK, > + .nr_clk_ids = CLKS_NR_PERIS, > .clk_regs = peris_clk_regs, > .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), > .clk_name = "dout_clkcmu_peris_bus", > -- > 2.34.1
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index ddef546be545..e9c06eb93e66 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -16,6 +16,17 @@ #include "clk.h" #include "clk-exynos-arm64.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1) +#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) +#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) +#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) +#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1) +#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1) + /* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x1b240000) */ @@ -941,7 +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; @@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(busmc_div_clks), .gate_clks = busmc_gate_clks, .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks), - .nr_clk_ids = BUSMC_NR_CLK, + .nr_clk_ids = CLKS_NR_BUSMC, .clk_regs = busmc_clk_regs, .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs), .clk_name = "dout_clkcmu_busmc_bus", @@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(core_div_clks), .gate_clks = core_gate_clks, .nr_gate_clks = ARRAY_SIZE(core_gate_clks), - .nr_clk_ids = CORE_NR_CLK, + .nr_clk_ids = CLKS_NR_CORE, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), .clk_name = "dout_clkcmu_core_bus", @@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = FSYS0_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS0, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), .clk_name = "dout_clkcmu_fsys0_bus", @@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), .gate_clks = fsys1_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), - .nr_clk_ids = FSYS1_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS1, .clk_regs = fsys1_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), .clk_name = "dout_clkcmu_fsys1_bus", @@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), .gate_clks = fsys2_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), - .nr_clk_ids = FSYS2_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS2, .clk_regs = fsys2_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), .clk_name = "dout_clkcmu_fsys2_bus", @@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric0_div_clks), .gate_clks = peric0_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), - .nr_clk_ids = PERIC0_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC0, .clk_regs = peric0_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), .clk_name = "dout_clkcmu_peric0_bus", @@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric1_div_clks), .gate_clks = peric1_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), - .nr_clk_ids = PERIC1_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC1, .clk_regs = peric1_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), .clk_name = "dout_clkcmu_peric1_bus", @@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), - .nr_clk_ids = PERIS_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIS, .clk_regs = peris_clk_regs, .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), .clk_name = "dout_clkcmu_peris_bus",
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore this number of clocks should not be in the bindings, because otherwise we should not change it. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-)