| Message ID | 20230810023548.412310-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement cortex-a710 | expand |
On Thu, 10 Aug 2023 at 03:36, Richard Henderson <richard.henderson@linaro.org> wrote: > > Self-hosted trace is out of scope for QEMU. True, but we already disable this in arm_cpu_realizefn() along with FEAT_SPE, FEAT_AMU and a bunch of other "out of scope" or not-yet-implemented features. I thought it more reliable to do the disabling globally rather than rely on everybody adding a new CPU to remember to adjust the ID register values. (Plus if we ever do implement some approximation to one of these features we only need to change one place in the code, not re-look-up all the CPU ID register values.) See commit 7d8c283e10dd81. thanks -- PMM
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8019f00bc3..60e5f034d9 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -618,7 +618,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize = 4; cpu->id_aa64afr0 = 0x00000000; cpu->id_aa64afr1 = 0x00000000; - cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; + cpu->isar.id_aa64dfr0 = 0x000000f210305519ull; /* w/o FEAT_TRF */ cpu->isar.id_aa64dfr1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ cpu->isar.id_aa64isar1 = 0x0111000001211032ull; @@ -628,7 +628,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; cpu->id_afr0 = 0x00000000; - cpu->isar.id_dfr0 = 0x15011099; + cpu->isar.id_dfr0 = 0x05011099; /* w/o FEAT_TRF */ cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar2 = 0x21232042;
Self-hosted trace is out of scope for QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/tcg/cpu64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)