From patchwork Thu Jul 7 18:49:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 71616 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp47902qgy; Thu, 7 Jul 2016 11:51:28 -0700 (PDT) X-Received: by 10.31.133.208 with SMTP id h199mr832204vkd.142.1467917488704; Thu, 07 Jul 2016 11:51:28 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f62si20621vkd.118.2016.07.07.11.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jul 2016 11:51:28 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bLEMP-0004q0-SM; Thu, 07 Jul 2016 18:49:17 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bLEMO-0004p1-Jx for xen-devel@lists.xen.org; Thu, 07 Jul 2016 18:49:16 +0000 Received: from [85.158.137.68] by server-6.bemta-3.messagelabs.com id 7D/3C-24961-B24AE775; Thu, 07 Jul 2016 18:49:15 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPLMWRWlGSWpSXmKPExsVysyfVTVd7SV2 4Qc80EYslHxezODB6HN39mymAMYo1My8pvyKBNePaoZtsBf8EK04cOs3cwDiJr4uRk0NIYCOj xOUJel2MXED2aUaJrzfWsoEk2AQ0Je58/sQEYosISEtc+3yZEaSIWaCNUWLt7KmMIAlhgSiJ8 992gBWxCKhKHLy4AyzOK+Ai8eZNAzuILSEgJ3Hy2GTWCYycCxgZVjFqFKcWlaUW6RpZ6iUVZa ZnlOQmZuboGhoY6+WmFhcnpqfmJCYV6yXn525iBHqsnoGBcQdj016/Q4ySHExKorwK/nXhQnx J+SmVGYnFGfFFpTmpxYcYZTg4lCR4axYD5QSLUtNTK9Iyc4ChA5OW4OBREuEtAknzFhck5hZn pkOkTjEqSonzxoEkBEASGaV5cG2wcL3EKCslzMvIwMAgxFOQWpSbWYIq/4pRnINRSZh3McgUn sy8Erjpr4AWMwEt/ulSDbK4JBEhJdXAWBN27MSBHdfctZjLdrIECDzJrHLgjt+bde7sMr2JZg 8Ni/6zrCgU4Tm0T+F7FIdU0+F91dcMGzi4vipYtT1x26gnVH/PNj1upqXQv/39C1tO+Wr0XmE paWS5bbPw5CST5MJ1nGEMgq/V+MUlamJSq+wmGzJ/Cfg9YbuxXWdj2ImHDj1rnIuVWIozEg21 mIuKEwG8h28gUgIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-12.tower-31.messagelabs.com!1467917354!32715366!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.46; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23480 invoked from network); 7 Jul 2016 18:49:15 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-12.tower-31.messagelabs.com with SMTP; 7 Jul 2016 18:49:15 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1469128; Thu, 7 Jul 2016 11:50:14 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.215.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 178DE3F41F; Thu, 7 Jul 2016 11:49:12 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 7 Jul 2016 19:49:08 +0100 Message-Id: <1467917348-24680-1-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, steve.capper@arm.com, wei.chen@linaro.org Subject: [Xen-devel] [PATCH v2] xen/arm64: Use the correct TLBs flush instruction to nuke stage-2 TLBs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The function flush_tlb is called to invalidate the TLBs for the current domain when the stage-2 page tables are modified. On ARMv8, the instruction "tlbi vmalle1is" (resp. "tlbi vmalle1") will invalidate stage 1 entries associated to the current VMID (see D4-1811 in ARM DDI 0487A.j). Given that an implementation is allowed to cache separately stage 1 and stage 2 translation (see D4.7.1), the instructions will not remove stage 2 entries when the translation is not combined in a single entry. This will result the TLBs to hold invalid entries and possibly multiple entries using the same VA. Use "tlbi vmalls12e1is" (resp. "tlbi vmalls12e1"), to flush both stage 1 and 2 entries when the domain p2m is changed. Also modify flush_tlb_local to invalidate stage 1 and 2 for the local TLBs. Note that this function is used in the instruction abort path before translating a GVA to a IPA. As far as I understand is to avoid a guest poisoning the DTLB when memacces is in use. We might be able to only invalidate stage 1 entries. However, I choose the safest way for now (i.e invalidating stage 1 and 2 entries). We would need to introduce a new set of helpers when we will want to restrict it. Signed-off-by: Julien Grall --- This would need to be backported on any version of Xen currently supported (IIRC think up to Xen 4.5). Without this patch, stage 2 TLBs won't be flushed if the TLBs cache intermediate translations entries (IPA -> PA). Changes in v2: - Fix instructions name in the commit message --- xen/include/asm-arm/arm64/flushtlb.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index a73df92..942f2d3 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -6,7 +6,7 @@ static inline void flush_tlb_local(void) { asm volatile( "dsb sy;" - "tlbi vmalle1;" + "tlbi vmalls12e1;" "dsb sy;" "isb;" : : : "memory"); @@ -17,7 +17,7 @@ static inline void flush_tlb(void) { asm volatile( "dsb sy;" - "tlbi vmalle1is;" + "tlbi vmalls12e1is;" "dsb sy;" "isb;" : : : "memory");