| Message ID | 20230825135503.282135-2-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Accepted |
| Commit | a5b5006edc6273c278930f0ee92773c13abd660e |
| Headers | show |
| Series | [1/2] dt-bindings: mmc: sdhci-msm: correct minimum number of clocks | expand |
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 10f34aa8ba8a..69a213965089 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -85,10 +85,10 @@ properties: - const: iface - const: core - const: xo - - const: ice - - const: bus - - const: cal - - const: sleep + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] dma-coherent: true
The Qualcomm SDHCI controller lists optional clocks, but still expects fixed order of them and does not allow to skip such clocks if further one in the list is needed. These optional clocks are truly optional, so we need to allow the list to have different orders. The clocks are: - ice: used for Inline Crypto Engine, which is actually separate block and merging it with SDHCI is not a requirement, - bus: clock for SDCC bus frequency voting, - cal and sleep: used for RCLK delay calibration and required for certain platforms for such calibration (as expressed in original commit 4946b3af5e8e ("mmc: sdhci-msm: Enable delay circuit calibration clocks")). Only MSM8974pro has these clocks. Relaxing the order fixes dtbs_check warnings: qcom-msm8974pro-fairphone-fp2.dtb: mmc@f9824900: clock-names:3: 'ice' was expected qcom-msm8974pro-fairphone-fp2.dtb: mmc@f9824900: clock-names:4: 'bus' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)