@@ -5098,8 +5098,7 @@ static int ufshcd_slave_configure(struct scsi_device *sdev)
struct request_queue *q = sdev->request_queue;
blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
- if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT)
- blk_queue_update_dma_alignment(q, SZ_4K - 1);
+
/*
* Block runtime-pm until all consumers are added.
* Refer ufshcd_setup_links().
@@ -5115,6 +5114,9 @@ static int ufshcd_slave_configure(struct scsi_device *sdev)
*/
sdev->silence_suspend = 1;
+ if (hba->vops && hba->vops->config_scsi_dev)
+ hba->vops->config_scsi_dev(sdev);
+
ufshcd_crypto_register(hba, q);
return 0;
@@ -1511,6 +1511,11 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
return 0;
}
+static void exynos_ufs_config_scsi_dev(struct scsi_device *sdev)
+{
+ blk_queue_update_dma_alignment(sdev->request_queue, SZ_4K - 1);
+}
+
static int fsd_ufs_post_link(struct exynos_ufs *ufs)
{
int i;
@@ -1579,6 +1584,7 @@ static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
.hibern8_notify = exynos_ufs_hibern8_notify,
.suspend = exynos_ufs_suspend,
.resume = exynos_ufs_resume,
+ .config_scsi_dev = exynos_ufs_config_scsi_dev,
};
static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
@@ -1680,8 +1686,7 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
- UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
- UFSHCD_QUIRK_4KB_DMA_ALIGNMENT,
+ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
.opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
@@ -28,6 +28,7 @@
#define UFSHCD "ufshcd"
+struct scsi_device;
struct ufs_hba;
enum dev_cmd_type {
@@ -371,6 +372,7 @@ struct ufs_hba_variant_ops {
int (*get_outstanding_cqs)(struct ufs_hba *hba,
unsigned long *ocqs);
int (*config_esi)(struct ufs_hba *hba);
+ void (*config_scsi_dev)(struct scsi_device *sdev);
};
/* clock gating state */
@@ -596,11 +598,6 @@ enum ufshcd_quirks {
*/
UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
- /*
- * Align DMA SG entries on a 4 KiB boundary.
- */
- UFSHCD_QUIRK_4KB_DMA_ALIGNMENT = 1 << 14,
-
/*
* This quirk needs to be enabled if the host controller does not
* support UIC command
The DMA alignment for the Exynos controller follows directly from the PRDT segment size configured in ufs-exynos.c. Hence, move the DMA alignment code into the Exynos driver source code. Cc: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Bart Van Assche <bvanassche@acm.org> --- drivers/ufs/core/ufshcd.c | 6 ++++-- drivers/ufs/host/ufs-exynos.c | 9 +++++++-- include/ufs/ufshcd.h | 7 ++----- 3 files changed, 13 insertions(+), 9 deletions(-)