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[209.132.180.131]) by mx.google.com with ESMTPS id pa7si23165767pac.177.2016.07.23.10.09.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Jul 2016 10:09:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gdb-patches-return-132737-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-132737-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-132737-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; q=dns; s= default; b=jiHoQQVdFmLUm9v8pawyO4nsHVqyAasYPPtJB51IdBpErGElEf7Os hM+rxyIDtkbITj1FRAyCTC58xlSFo9Z7m95ncV49w2vUB97/gQ5nviBTzkC8kEOs VCok55yk2lr2iSiVBHpauL8HyHqd+hGN+5ZyKbU1Z2nX/g+isMPumE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; s=default; bh=+LgCWc6VXonjI7U3AZE/jeeeFRg=; b=DHuHLpQZ8TaYxO/HDJeUbgIFHGSp 1k3zZBOIjtK2iWXa4MojeuPoQHSCcgSyUgcL04pX1IKPUF57v/OjtPseBhnRPSeN z49uNPhQyg86dOXXNlif22k6M1f5GNysbIDACkQzZVnoS+skG6mVjs8Fp3AbUQv7 SYM1ncCyt5NWZ1U= Received: (qmail 54843 invoked by alias); 23 Jul 2016 17:09:12 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 54823 invoked by uid 89); 23 Jul 2016 17:09:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=iov, H*Ad:D*cavium.com, 6529, 2016-07-23 X-HELO: camailhost.cavium.com Received: from camailhost.cavium.com (HELO camailhost.cavium.com) (12.108.191.230) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sat, 23 Jul 2016 17:09:01 +0000 Received: from apinski-ss1.caveonetworks.com ([10.18.106.6]) by camailhost.cavium.com (8.14.7/8.14.7) with ESMTP id u6NH8up2002818; Sat, 23 Jul 2016 10:08:56 -0700 Received: from apinski-ss1.caveonetworks.com (localhost [127.0.0.1]) by apinski-ss1.caveonetworks.com (8.15.2/8.15.2/Debian-3) with ESMTP id u6NH8uwx023405; Sat, 23 Jul 2016 10:08:56 -0700 Received: (from apinski@localhost) by apinski-ss1.caveonetworks.com (8.15.2/8.15.2/Submit) id u6NH8uqB023404; Sat, 23 Jul 2016 10:08:56 -0700 From: Andrew Pinski To: gdb-patches@sourceware.org Cc: Andrew Pinski Subject: [PATCH] Fix ARMv8.1/v8.2 for hw watchpoint and breakpoint Date: Sat, 23 Jul 2016 10:08:43 -0700 Message-Id: <1469293723-23352-1-git-send-email-apinski@cavium.com> The problem here is ARMv8.1 (and ARMv8.2) define a different debug version than ARMv8 (7 and 8 respectively). This fixes hw watchpoints and breakpoints by checking for those debug versions too. Committed as obvious after a test on aarch64-linux-gnu (on a ThunderX machine which has ARMv8.1 support enabled). ChangeLog: * nat/aarch64-linux-hw-point.c (aarch64_linux_get_debug_reg_capacity): Handle ARMv8.1 and ARMv8.2 debug versions. * nat/aarch64-linux-hw-point.h (AARCH64_DEBUG_ARCH_V8_1): New define. (AARCH64_DEBUG_ARCH_V8_2): New define. Signed-off-by: Andrew Pinski --- gdb/ChangeLog | 9 +++++++++ gdb/nat/aarch64-linux-hw-point.c | 8 ++++++-- gdb/nat/aarch64-linux-hw-point.h | 2 ++ 3 files changed, 17 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 014c0bf..490320e 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,12 @@ +2016-07-23 Andrew Pinski + + * nat/aarch64-linux-hw-point.c + (aarch64_linux_get_debug_reg_capacity): Handle + ARMv8.1 and ARMv8.2 debug versions. + * nat/aarch64-linux-hw-point.h + (AARCH64_DEBUG_ARCH_V8_1): New define. + (AARCH64_DEBUG_ARCH_V8_2): New define. + 2016-07-22 Tom Tromey PR rust/20162: diff --git a/gdb/nat/aarch64-linux-hw-point.c b/gdb/nat/aarch64-linux-hw-point.c index a06a6e6..f9e04d9 100644 --- a/gdb/nat/aarch64-linux-hw-point.c +++ b/gdb/nat/aarch64-linux-hw-point.c @@ -630,7 +630,9 @@ aarch64_linux_get_debug_reg_capacity (int tid) /* Get hardware watchpoint register info. */ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 - && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) + && (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8 + || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1 + || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2)) { aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) @@ -650,7 +652,9 @@ aarch64_linux_get_debug_reg_capacity (int tid) /* Get hardware breakpoint register info. */ if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 - && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) + && (AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8 + || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_1 + || AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8_2)) { aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) diff --git a/gdb/nat/aarch64-linux-hw-point.h b/gdb/nat/aarch64-linux-hw-point.h index acf0a49..16efb7c 100644 --- a/gdb/nat/aarch64-linux-hw-point.h +++ b/gdb/nat/aarch64-linux-hw-point.h @@ -68,6 +68,8 @@ /* Macro for the expected version of the ARMv8-A debug architecture. */ #define AARCH64_DEBUG_ARCH_V8 0x6 +#define AARCH64_DEBUG_ARCH_V8_1 0x7 +#define AARCH64_DEBUG_ARCH_V8_2 0x8 /* ptrace expects control registers to be formatted as follows: