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[192.237.175.120]) by mx.google.com with ESMTPS id g140si7477368itg.49.2016.07.27.07.01.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jul 2016 07:01:30 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPMD-0006Il-Ea; Wed, 27 Jul 2016 13:58:45 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPMC-0006I8-2L for xen-devel@lists.xen.org; Wed, 27 Jul 2016 13:58:44 +0000 Received: from [193.109.254.147] by server-10.bemta-14.messagelabs.com id 62/10-03469-31EB8975; Wed, 27 Jul 2016 13:58:43 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTVdo34x wgxeLVC2WfFzM4sDocXT3b6YAxijWzLyk/IoE1ow/Hw+xFWwyqng8YRdTA+Nk9S5GLg4hgY2M En/vTWKCcE4zStzetputi5GTg01AU+LO509MILaIgLTEtc+XGUFsZoGFjBJvd4eA2MICdhJn7 h5g72Lk4GARUJXYfK0UxOQVcJZon8QPUiEhICdx8thkVhCbU8BFovfSJbApQkAlZ/5uZJ3AyL 2AkWEVo0ZxalFZapGuobleUlFmekZJbmJmjq6hoYlebmpxcWJ6ak5iUrFecn7uJkagd+sZGBh 3MP487XmIUZKDSUmUd5HjjHAhvqT8lMqMxOKM+KLSnNTiQ4wyHBxKErw39wDlBItS01Mr0jJz gGEGk5bg4FES4Z25GyjNW1yQmFucmQ6ROsWoKCXOK7AXKCEAksgozYNrg4X2JUZZKWFeRgYGB iGegtSi3MwSVPlXjOIcjErCvD9AtvNk5pXATX8FtJgJaHFxLNjikkSElFQD44Lw2u26qZILrT 7+mrGYcZ+W4MvnmkcCf1dyTdvxQybeYo5C5LevS8oC/8U/fNc8uTOmX9ry1xp9kYtVX9bczuC eMX9WgtV1vRe1E9da3n2z2qRbpK/L3/BG9ek5F4OdP9wys2l4t7d71wSfbTeUfbzjv+aX/mxP 7f+7/taNrNIl0evaZXkeSCuxFGckGmoxFxUnAgCzAXwqaAIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-5.tower-27.messagelabs.com!1469627921!56277183!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8935 invoked from network); 27 Jul 2016 13:58:42 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-27.messagelabs.com with SMTP; 27 Jul 2016 13:58:42 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C4E322F; Wed, 27 Jul 2016 06:59:57 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4AEFF3F25F; Wed, 27 Jul 2016 06:58:40 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 27 Jul 2016 14:58:24 +0100 Message-Id: <1469627910-3902-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469627910-3902-1-git-send-email-julien.grall@arm.com> References: <1469627910-3902-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, steve.capper@arm.com, Julien Grall , shannon.zhao@linaro.org, shankerd@codeaurora.org, wei.chen@linaro.org Subject: [Xen-devel] [PATCH v3 3/9] xen/arm: gic: split set_irq_properties X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The callback set_irq_properties will configure the GIC for a specific IRQ with the type and the priority. In a follow-up patch, Xen will configure the type and the priority at different stage of the routing. So split it in 2 separate callbacks. At the same time, move the ASSERT to check the validity of the type and if the desc->lock is locked in the common code (gic.c). This is because the constraint are the same between GICv2 and GICv3, however the driver of the latter did not contain any sanity check. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Stefano's reviewed-by --- xen/arch/arm/gic-v2.c | 19 +++++++++++++------ xen/arch/arm/gic-v3.c | 15 ++++++++++++--- xen/arch/arm/gic.c | 23 ++++++++++++++--------- xen/include/asm-arm/gic.h | 7 ++++--- 4 files changed, 43 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 6c7dbfe..69ed72d 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -236,16 +236,12 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } -static void gicv2_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gicv2_set_irq_type(struct irq_desc *desc) { uint32_t cfg, actual, edgebit; unsigned int irq = desc->irq; unsigned int type = desc->arch.type; - ASSERT(type != IRQ_TYPE_INVALID); - ASSERT(spin_is_locked(&desc->lock)); - spin_lock(&gicv2.lock); /* Set edge / level */ cfg = readl_gicd(GICD_ICFGR + (irq / 16) * 4); @@ -270,6 +266,16 @@ static void gicv2_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_LEVEL_HIGH; } + spin_unlock(&gicv2.lock); +} + +static void gicv2_set_irq_priority(struct irq_desc *desc, + unsigned int priority) +{ + unsigned int irq = desc->irq; + + spin_lock(&gicv2.lock); + /* Set priority */ writeb_gicd(priority, GICD_IPRIORITYR + irq); @@ -1217,7 +1223,8 @@ const static struct gic_hw_operations gicv2_ops = { .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, - .set_irq_properties = gicv2_set_irq_properties, + .set_irq_type = gicv2_set_irq_type, + .set_irq_priority = gicv2_set_irq_priority, .send_SGI = gicv2_send_SGI, .disable_interface = gicv2_disable_interface, .update_lr = gicv2_update_lr, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index d6ab0e9..781f25c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -471,8 +471,7 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu) MPIDR_AFFINITY_LEVEL(mpidr, 0)); } -static void gicv3_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gicv3_set_irq_type(struct irq_desc *desc) { uint32_t cfg, actual, edgebit; void __iomem *base; @@ -512,6 +511,15 @@ static void gicv3_set_irq_properties(struct irq_desc *desc, IRQ_TYPE_EDGE_RISING : IRQ_TYPE_LEVEL_HIGH; } + spin_unlock(&gicv3.lock); +} + +static void gicv3_set_irq_priority(struct irq_desc *desc, + unsigned int priority) +{ + unsigned int irq = desc->irq; + + spin_lock(&gicv3.lock); /* Set priority */ if ( irq < NR_GIC_LOCAL_IRQS ) @@ -1579,7 +1587,8 @@ static const struct gic_hw_operations gicv3_ops = { .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, - .set_irq_properties = gicv3_set_irq_properties, + .set_irq_type = gicv3_set_irq_type, + .set_irq_priority = gicv3_set_irq_priority, .send_SGI = gicv3_send_sgi, .disable_interface = gicv3_disable_interface, .update_lr = gicv3_update_lr, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bc814a0..c63c862 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -96,14 +96,17 @@ void gic_restore_state(struct vcpu *v) gic_restore_pending_irqs(v); } -/* - * - desc.lock must be held - * - arch.type must be valid (i.e != IRQ_TYPE_INVALID) - */ -static void gic_set_irq_properties(struct irq_desc *desc, - unsigned int priority) +static void gic_set_irq_type(struct irq_desc *desc) +{ + ASSERT(spin_is_locked(&desc->lock)); + ASSERT(desc->arch.type != IRQ_TYPE_INVALID); + + gic_hw_ops->set_irq_type(desc); +} + +static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority) { - gic_hw_ops->set_irq_properties(desc, priority); + gic_hw_ops->set_irq_priority(desc, priority); } /* Program the GIC to route an interrupt to the host (i.e. Xen) @@ -118,7 +121,8 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) desc->handler = gic_hw_ops->gic_host_irq_type; - gic_set_irq_properties(desc, priority); + gic_set_irq_type(desc); + gic_set_irq_priority(desc, priority); } /* Program the GIC to route an interrupt to a guest @@ -150,7 +154,8 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); - gic_set_irq_properties(desc, priority); + gic_set_irq_type(desc); + gic_set_irq_priority(desc, priority); p->desc = desc; res = 0; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 7ba3846..3f39f79 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -328,9 +328,10 @@ struct gic_hw_operations { void (*deactivate_irq)(struct irq_desc *irqd); /* Read IRQ id and Ack */ unsigned int (*read_irq)(void); - /* Set IRQ property */ - void (*set_irq_properties)(struct irq_desc *desc, - unsigned int priority); + /* Set IRQ type - type is taken from desc->arch.type */ + void (*set_irq_type)(struct irq_desc *desc); + /* Set IRQ priority */ + void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority); /* Send SGI */ void (*send_SGI)(enum gic_sgi sgi, enum gic_sgi_mode irqmode, const cpumask_t *online_mask);