From patchwork Wed Jul 27 13:58:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 72876 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp328937qga; Wed, 27 Jul 2016 07:01:36 -0700 (PDT) X-Received: by 10.36.39.195 with SMTP id g186mr30699623ita.53.1469628091884; Wed, 27 Jul 2016 07:01:31 -0700 (PDT) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 2si7480452itg.57.2016.07.27.07.01.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jul 2016 07:01:30 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPMB-0006Ho-3V; Wed, 27 Jul 2016 13:58:43 +0000 Received: from mail6.bemta6.messagelabs.com ([85.158.143.247]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSPMA-0006HP-9G for xen-devel@lists.xen.org; Wed, 27 Jul 2016 13:58:42 +0000 Received: from [85.158.143.35] by server-1.bemta-6.messagelabs.com id 22/F2-21406-11EB8975; Wed, 27 Jul 2016 13:58:41 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrKLMWRWlGSWpSXmKPExsVysyfVTVdw34x wg3nXWS2WfFzM4sDocXT3b6YAxijWzLyk/IoE1ozNLe/YC/4pVqx6GNzAOFOqi5GLQ0hgI6PE y+WtbBDOaUaJy6c7WboYOTnYBDQl7nz+xARiiwhIS1z7fJkRxGYWWMgo8XZ3CIgtLOAncXreG XYQm0VAVWL9u9/MIDavgLPElikQcQkBOYmTxyazgticAi4SvZcugc0RAqo583cj6wRG7gWMDK sY1YtTi8pSi3RN9ZKKMtMzSnITM3N0DQ3M9HJTi4sT01NzEpOK9ZLzczcxAr3LAAQ7GKdf9j/ EKMnBpCTKu8hxRrgQX1J+SmVGYnFGfFFpTmrxIUYZDg4lCd6be4BygkWp6akVaZk5wDCDSUtw 8CiJ8M7cDZTmLS5IzC3OTIdInWJUlBLnFdgLlBAASWSU5sG1wUL7EqOslDAvI9AhQjwFqUW5m SWo8q8YxTkYlYR5f4Bs58nMK4Gb/gpoMRPQ4uJYsMUliQgpqQbGoyIaEsunids68OyYWzVXKC kugbO0TtAjIi1IaX76G0WGDUdLLPgrj7Ft2Wb0TlB0e9uPR9pvDl30K1q+0V61+//2winrdk8 Pjp0c/PRp7ftnJXNjc4v9n+g4hgTmu5tOEJ0qtLBm52LLF5HyzzbNeyb+7Tvb3Myrd8s6ayJM Q1OvHm9iUzmjxFKckWioxVxUnAgADwI2y2gCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1469627920!21459702!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 60392 invoked from network); 27 Jul 2016 13:58:40 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-16.tower-21.messagelabs.com with SMTP; 27 Jul 2016 13:58:40 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51FAD28; Wed, 27 Jul 2016 06:59:56 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CBC583F25F; Wed, 27 Jul 2016 06:58:38 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 27 Jul 2016 14:58:23 +0100 Message-Id: <1469627910-3902-3-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469627910-3902-1-git-send-email-julien.grall@arm.com> References: <1469627910-3902-1-git-send-email-julien.grall@arm.com> Cc: sstabellini@kernel.org, steve.capper@arm.com, Julien Grall , shannon.zhao@linaro.org, shankerd@codeaurora.org, wei.chen@linaro.org Subject: [Xen-devel] [PATCH v3 2/9] xen/arm: gic: Do not configure affinity during routing X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The affinity of a guest IRQ is set every time the guest enable it (see vgic_enable_irqs). It is not necessary to set the affinity when the IRQ is routed to the guest because Xen will never receive the IRQ until it hass been enabled by the guest. To keep gic_route_irq_to_{xen,guest} behaving the same way (i.e just setting up the routing), the affinity of IRQ routed to Xen is moved into __setup_irq. Signed-off-by: Julien grall Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by Changes in v2: - Patch renamed - Set the affinity for IRQ routed to Xen in __setup_irq --- xen/arch/arm/gic.c | 11 +++-------- xen/arch/arm/irq.c | 4 ++-- xen/include/asm-arm/gic.h | 3 +-- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 5726a05..bc814a0 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -97,24 +97,19 @@ void gic_restore_state(struct vcpu *v) } /* - * needs to be called with a valid cpu_mask, ie each cpu in the mask has - * already called gic_cpu_init * - desc.lock must be held * - arch.type must be valid (i.e != IRQ_TYPE_INVALID) */ static void gic_set_irq_properties(struct irq_desc *desc, - const cpumask_t *cpu_mask, unsigned int priority) { gic_hw_ops->set_irq_properties(desc, priority); - desc->handler->set_affinity(desc, cpu_mask); } /* Program the GIC to route an interrupt to the host (i.e. Xen) * - needs to be called with desc.lock held */ -void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, - unsigned int priority) +void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) { ASSERT(priority <= 0xff); /* Only 8 bits of priority */ ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */ @@ -123,7 +118,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, desc->handler = gic_hw_ops->gic_host_irq_type; - gic_set_irq_properties(desc, cpu_mask, priority); + gic_set_irq_properties(desc, priority); } /* Program the GIC to route an interrupt to a guest @@ -155,7 +150,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); - gic_set_irq_properties(desc, cpumask_of(v_target->processor), priority); + gic_set_irq_properties(desc, priority); p->desc = desc; res = 0; diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 2f8af72..3fc22f2 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -370,6 +370,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) /* First time the IRQ is setup */ if ( disabled ) { + gic_route_irq_to_xen(desc, GIC_PRI_IRQ); /* It's fine to use smp_processor_id() because: * For PPI: irq_desc is banked * For SPI: we don't care for now which CPU will receive the @@ -377,8 +378,7 @@ int setup_irq(unsigned int irq, unsigned int irqflags, struct irqaction *new) * TODO: Handle case where SPI is setup on different CPU than * the targeted CPU and the priority. */ - gic_route_irq_to_xen(desc, cpumask_of(smp_processor_id()), - GIC_PRI_IRQ); + irq_set_affinity(desc, cpumask_of(smp_processor_id())); desc->handler->startup(desc); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 2fc6126..7ba3846 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -223,8 +223,7 @@ enum gic_version { extern enum gic_version gic_hw_version(void); /* Program the GIC to route an interrupt */ -extern void gic_route_irq_to_xen(struct irq_desc *desc, const cpumask_t *cpu_mask, - unsigned int priority); +extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, struct irq_desc *desc, unsigned int priority);