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[192.237.175.120]) by mx.google.com with ESMTPS id f74si8142683iod.184.2016.07.27.09.39.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jul 2016 09:39:39 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSRpj-0001LG-MY; Wed, 27 Jul 2016 16:37:23 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bSRpi-0001Jh-En for xen-devel@lists.xen.org; Wed, 27 Jul 2016 16:37:22 +0000 Received: from [85.158.139.211] by server-15.bemta-5.messagelabs.com id A5/ED-12460-143E8975; Wed, 27 Jul 2016 16:37:21 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTdfx8Yx wgwObhSyWfFzM4sDocXT3b6YAxijWzLyk/IoE1ozz25exFnRoVCw9P4mlgfGAQhcjJ4eQwEZG ieZpPF2MXED2aUaJpgXN7CAJNgFNiTufPzGB2CIC0hLXPl9mBLGZBSIlnsy8wQxiCwuESsx5e ogFxGYRUJX41XoKrJdXwFli6tE7YLaEgJzEyWOTWUFsTgEXiR+TfrFBLHaW+LbvMfMERu4FjA yrGDWKU4vKUot0jYz0kooy0zNKchMzc3QNDUz1clOLixPTU3MSk4r1kvNzNzEC/VvPwMC4g3F Pu98hRkkOJiVR3kWOM8KF+JLyUyozEosz4otKc1KLDzHKcHAoSfB+fgiUEyxKTU+tSMvMAQYa TFqCg0dJhFfhEVCat7ggMbc4Mx0idYpRUUqc9wtInwBIIqM0D64NFtyXGGWlhHkZGRgYhHgKU otyM0tQ5V8xinMwKgnzyoOM58nMK4Gb/gpoMRPQ4uJYsMUliQgpqQZG6e/nonRdz85JMS3gFx Y/+fDd3mnfpiz8JFz9b3NwSljH9Nvrpr5zjAo++vhQ0ptG1asPoywFquxzLhy02eekwu+nJWV y5GmPvEowd4HhAdUJHw5Y/L5Y2z1zs9OsL0Ymq5iOsKxUbele+fkS9+dt693bE2a9NbVj4PdP dWNYllC3p1ZD9A2HEktxRqKhFnNRcSIAQ7VXYmkCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1469637440!39617169!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 8.77; banners=-,-,- X-VirusChecked: Checked Received: (qmail 33442 invoked from network); 27 Jul 2016 16:37:20 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-206.messagelabs.com with SMTP; 27 Jul 2016 16:37:20 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF01D2F; Wed, 27 Jul 2016 09:38:36 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9869A3F25F; Wed, 27 Jul 2016 09:37:19 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 27 Jul 2016 17:37:07 +0100 Message-Id: <1469637431-1069-4-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469637431-1069-1-git-send-email-julien.grall@arm.com> References: <1469637431-1069-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v6 3/7] xen/arm: Detect silicon revision and set cap bits accordingly X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" After each CPU has been started, we iterate through a list of CPU errata to detect CPUs which need from hypervisor code patches. For each bug there is a function which checks if that a particular CPU is affected. This needs to be done on every CPU to cover heterogenous systems properly. If a certain erratum has been detected, the capability bit will be set. In the case the erratum requires code patching, this will be triggered by the call to apply_alternatives. The code is based on the file arch/arm64/kernel/cpu_errata.c in Linux v4.6-rc3. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- Changes in v6: - Fix typoes in the commit message - Add __ to the guard Changes in v4: - Add missing emacs magic blocks - Add Stefano's acked-by Changes in v3: - Move update_cpu_capabilities in a separate patch - Update the commit message to mention that workaround may not require code patching. Changes in v2: - Use XENLOG_INFO for the loglevel of the message --- xen/arch/arm/Makefile | 1 + xen/arch/arm/cpuerrata.c | 34 ++++++++++++++++++++++++++++++++++ xen/arch/arm/setup.c | 3 +++ xen/arch/arm/smpboot.c | 3 +++ xen/include/asm-arm/cpuerrata.h | 14 ++++++++++++++ xen/include/asm-arm/cpufeature.h | 6 ++++++ 6 files changed, 61 insertions(+) create mode 100644 xen/arch/arm/cpuerrata.c create mode 100644 xen/include/asm-arm/cpuerrata.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 74bd7b8..23aaf52 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -7,6 +7,7 @@ subdir-$(CONFIG_ACPI) += acpi obj-$(CONFIG_ALTERNATIVE) += alternative.o obj-y += bootfdt.o obj-y += cpu.o +obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o obj-y += device.o diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c new file mode 100644 index 0000000..03ae7b4 --- /dev/null +++ b/xen/arch/arm/cpuerrata.c @@ -0,0 +1,34 @@ +#include +#include +#include + +#define MIDR_RANGE(model, min, max) \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = min, \ + .midr_range_max = max + +static bool_t __maybe_unused +is_affected_midr_range(const struct arm_cpu_capabilities *entry) +{ + return MIDR_IS_CPU_MODEL_RANGE(boot_cpu_data.midr.bits, entry->midr_model, + entry->midr_range_min, + entry->midr_range_max); +} + +static const struct arm_cpu_capabilities arm_errata[] = { + {}, +}; + +void check_local_cpu_errata(void) +{ + update_cpu_capabilities(arm_errata, "enabled workaround for"); +} +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 97b3214..38eb888 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,8 @@ static void __init processor_id(void) } processor_setup(); + + check_local_cpu_errata(); } void dt_unreserved_regions(paddr_t s, paddr_t e, diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 3a962f7..d56b91d 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -316,6 +317,8 @@ void start_secondary(unsigned long boot_phys_offset, local_irq_enable(); local_abort_enable(); + check_local_cpu_errata(); + printk(XENLOG_DEBUG "CPU %u booted.\n", smp_processor_id()); startup_cpu_idle_loop(); diff --git a/xen/include/asm-arm/cpuerrata.h b/xen/include/asm-arm/cpuerrata.h new file mode 100644 index 0000000..c495ee5 --- /dev/null +++ b/xen/include/asm-arm/cpuerrata.h @@ -0,0 +1,14 @@ +#ifndef __ARM_CPUERRATA_H__ +#define __ARM_CPUERRATA_H__ + +void check_local_cpu_errata(void); + +#endif /* __ARM_CPUERRATA_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index be2414c..fb57295 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -66,6 +66,12 @@ struct arm_cpu_capabilities { const char *desc; u16 capability; bool_t (*matches)(const struct arm_cpu_capabilities *); + union { + struct { /* To be used for eratum handling only */ + u32 midr_model; + u32 midr_range_min, midr_range_max; + }; + }; }; void update_cpu_capabilities(const struct arm_cpu_capabilities *caps,