From patchwork Mon Aug 1 08:12:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 73096 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp2571774qga; Mon, 1 Aug 2016 01:11:45 -0700 (PDT) X-Received: by 10.66.248.10 with SMTP id yi10mr84239702pac.31.1470039105110; Mon, 01 Aug 2016 01:11:45 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u66si33966647pfa.108.2016.08.01.01.11.44; Mon, 01 Aug 2016 01:11:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751178AbcHAILm (ORCPT + 7 others); Mon, 1 Aug 2016 04:11:42 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:17790 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751162AbcHAILl (ORCPT ); Mon, 1 Aug 2016 04:11:41 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id u718AZis005452; Mon, 1 Aug 2016 17:10:35 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u718AZis005452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1470039036; bh=1wyW1mgHRdxid0yjjQZmvnbqm/5pa1yJL57JvdfxdP0=; h=From:To:Cc:Subject:Date:From; b=Q/0+bCdxdTeRDSI+whfvk5lZS5ZVNNImccsG2IwqBjlb9fYeKQ3kPFMo+sfLgd/Nd PmiGUnsfxdfnSNvkoOMuBp48mf1fN/Cgo/dCmHkwfeenD5793+Qfy+C4anIRH+my+H fRNnhunxPGzUYHANAW+x2RVEvHofq6AcAQzhoGtMlxhca9qHBwVMCXynlLOxjy9Psw tZC+CEdSEzxXfG4P0mpULK84TRN8hHsQpIk91r52xhvw3hyUhfgiD4qP81xOLfs5I5 VEGnNH4liQ73waO2gpclLkhnhpehXipIAYHPvYmNbTZ2pFJ4A4huSwhd7zgGgZizjv hJrFErz3BoeZw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: arm@kernel.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas , linux-arm-kernel@lists.infradead.org Subject: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer Date: Mon, 1 Aug 2016 17:12:20 +0900 Message-Id: <1470039140-3801-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit 1e2a7d78499e ("irqdomain: Don't set type when mapping an IRQ"), the interrupt type is strictly checked. Without this patch, this board would not boot any more. Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt says that the 3rd cell should be either 1 (edge) or 4 (level) depending on the trigger type. As the CA72 Generic Timer provides active-low interrupts, the value of the 3rd cell should be 4. Signed-off-by: Masahiro Yamada Suggested-by: Marc Zyngier --- Arnd, Olof, I guess you are about to send pull-reqs for v4.8 cycle. Could you include this one in them? After IRQ updates for 4.8 were merged, my board would not boot at all. I consulted experts and looks like my DT was wrong. I could do this after -rc1 is out because it is apparently a bug fix, but in that case the for-next branch in ASOC will be broken for me, which would make bisect-ability difficult for me. arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index fd1af50..bafbcce 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -117,10 +117,7 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; soc {