diff mbox series

[06/18] target/loongarch: Declare QOM definitions in 'cpu-qom.h'

Message ID 20231010092901.99189-7-philmd@linaro.org
State New
Headers show
Series target: Make 'cpu-qom.h' really target agnostic | expand

Commit Message

Philippe Mathieu-Daudé Oct. 10, 2023, 9:28 a.m. UTC 
"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/cpu-qom.h | 38 ++++++++++++++++++++++++++++++++++++++
 target/loongarch/cpu.h     | 26 +-------------------------
 2 files changed, 39 insertions(+), 25 deletions(-)
 create mode 100644 target/loongarch/cpu-qom.h

Comments

gaosong Oct. 10, 2023, 11:33 a.m. UTC | #1 
在 2023/10/10 下午5:28, Philippe Mathieu-Daudé 写道:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/loongarch/cpu-qom.h | 38 ++++++++++++++++++++++++++++++++++++++
>   target/loongarch/cpu.h     | 26 +-------------------------
>   2 files changed, 39 insertions(+), 25 deletions(-)
>   create mode 100644 target/loongarch/cpu-qom.h
> 
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao

> diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
> new file mode 100644
> index 0000000000..d577af9f6e
> --- /dev/null
> +++ b/target/loongarch/cpu-qom.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch CPU QOM header (target agnostic)
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef LOONGARCH_CPU_QOM_H
> +#define LOONGARCH_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_LOONGARCH_CPU "loongarch-cpu"
> +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
> +
> +OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
> +                        LOONGARCH_CPU)
> +
> +#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> +#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
> +
> +/**
> + * LoongArchCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A LoongArch CPU model.
> + */
> +struct LoongArchCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
> +#endif
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 40e70a8119..22cebc6280 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -17,6 +17,7 @@
>   #include "exec/memory.h"
>   #endif
>   #include "cpu-csr.h"
> +#include "cpu-qom.h"
>   
>   #define IOCSRF_TEMP             0
>   #define IOCSRF_NODECNT          1
> @@ -383,29 +384,6 @@ struct ArchCPU {
>       const char *dtb_compatible;
>   };
>   
> -#define TYPE_LOONGARCH_CPU "loongarch-cpu"
> -#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> -#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
> -
> -OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
> -                        LOONGARCH_CPU)
> -
> -/**
> - * LoongArchCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A LoongArch CPU model.
> - */
> -struct LoongArchCPUClass {
> -    /*< private >*/
> -    CPUClass parent_class;
> -    /*< public >*/
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
>   /*
>    * LoongArch CPUs has 4 privilege levels.
>    * 0 for kernel mode, 3 for user mode.
> @@ -482,8 +460,6 @@ void loongarch_cpu_list(void);
>   
>   #include "exec/cpu-all.h"
>   
> -#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> -#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
>   
>   #endif /* LOONGARCH_CPU_H */
>
diff mbox series

Patch

diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
new file mode 100644
index 0000000000..d577af9f6e
--- /dev/null
+++ b/target/loongarch/cpu-qom.h
@@ -0,0 +1,38 @@ 
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_QOM_H
+#define LOONGARCH_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_LOONGARCH_CPU "loongarch-cpu"
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
+                        LOONGARCH_CPU)
+
+#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
+#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
+
+/**
+ * LoongArchCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A LoongArch CPU model.
+ */
+struct LoongArchCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+#endif
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 40e70a8119..22cebc6280 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -17,6 +17,7 @@ 
 #include "exec/memory.h"
 #endif
 #include "cpu-csr.h"
+#include "cpu-qom.h"
 
 #define IOCSRF_TEMP             0
 #define IOCSRF_NODECNT          1
@@ -383,29 +384,6 @@  struct ArchCPU {
     const char *dtb_compatible;
 };
 
-#define TYPE_LOONGARCH_CPU "loongarch-cpu"
-#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
-#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
-                        LOONGARCH_CPU)
-
-/**
- * LoongArchCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A LoongArch CPU model.
- */
-struct LoongArchCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 /*
  * LoongArch CPUs has 4 privilege levels.
  * 0 for kernel mode, 3 for user mode.
@@ -482,8 +460,6 @@  void loongarch_cpu_list(void);
 
 #include "exec/cpu-all.h"
 
-#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
-#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
 
 #endif /* LOONGARCH_CPU_H */