| Message ID | 20231013140116.255-4-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target: Make 'cpu-qom.h' really target agnostic | expand |
On 10/13/23 07:01, Philippe Mathieu-Daudé wrote: > These definitions and declarations are only used by > target/arm/, no need to expose them to generic hw/. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/arm/cpu-qom.h | 28 ---------------------------- > target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ > 2 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index dfb9d5b827..35c3b0924e 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo { > void (*class_init)(ObjectClass *oc, void *data); > } ARMCPUInfo; > > -void arm_cpu_register(const ARMCPUInfo *info); > -void aarch64_cpu_register(const ARMCPUInfo *info); > - > /** > * ARMCPUClass: > * @parent_realize: The parent class' realize handler. > @@ -63,29 +60,4 @@ struct AArch64CPUClass { > ARMCPUClass parent_class; > }; > > -void register_cp_regs_for_features(ARMCPU *cpu); > -void init_cpreg_list(ARMCPU *cpu); > - > -/* Callback functions for the generic timer's timers. */ > -void arm_gt_ptimer_cb(void *opaque); > -void arm_gt_vtimer_cb(void *opaque); > -void arm_gt_htimer_cb(void *opaque); > -void arm_gt_stimer_cb(void *opaque); > -void arm_gt_hvtimer_cb(void *opaque); > - > -#define ARM_AFF0_SHIFT 0 > -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) > -#define ARM_AFF1_SHIFT 8 > -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) > -#define ARM_AFF2_SHIFT 16 > -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) > -#define ARM_AFF3_SHIFT 32 > -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) > -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 > - > -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) > -#define ARM64_AFFINITY_MASK \ > - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) > -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) > - > #endif > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index fb1b08371c..06f92dacb9 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1116,11 +1116,39 @@ struct ArchCPU { > uint64_t gt_cntfrq_hz; > }; > > +/* Callback functions for the generic timer's timers. */ > +void arm_gt_ptimer_cb(void *opaque); > +void arm_gt_vtimer_cb(void *opaque); > +void arm_gt_htimer_cb(void *opaque); > +void arm_gt_stimer_cb(void *opaque); > +void arm_gt_hvtimer_cb(void *opaque); > + > unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); > void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); > > void arm_cpu_post_init(Object *obj); > > +void arm_cpu_register(const ARMCPUInfo *info); > +void aarch64_cpu_register(const ARMCPUInfo *info); > + > +void register_cp_regs_for_features(ARMCPU *cpu); > +void init_cpreg_list(ARMCPU *cpu); These can go to internals.h. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > + > +#define ARM_AFF0_SHIFT 0 > +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) > +#define ARM_AFF1_SHIFT 8 > +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) > +#define ARM_AFF2_SHIFT 16 > +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) > +#define ARM_AFF3_SHIFT 32 > +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) > +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 > + > +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) > +#define ARM64_AFFINITY_MASK \ > + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) > +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) > + > uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); > > #ifndef CONFIG_USER_ONLY
On 13/10/23 16:27, Richard Henderson wrote: > On 10/13/23 07:01, Philippe Mathieu-Daudé wrote: >> These definitions and declarations are only used by >> target/arm/, no need to expose them to generic hw/. >> >> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> >> --- >> target/arm/cpu-qom.h | 28 ---------------------------- >> target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 28 insertions(+), 28 deletions(-) >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index fb1b08371c..06f92dacb9 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -1116,11 +1116,39 @@ struct ArchCPU { >> uint64_t gt_cntfrq_hz; >> }; >> +/* Callback functions for the generic timer's timers. */ >> +void arm_gt_ptimer_cb(void *opaque); >> +void arm_gt_vtimer_cb(void *opaque); >> +void arm_gt_htimer_cb(void *opaque); >> +void arm_gt_stimer_cb(void *opaque); >> +void arm_gt_hvtimer_cb(void *opaque); >> + >> unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); >> void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); >> void arm_cpu_post_init(Object *obj); >> +void arm_cpu_register(const ARMCPUInfo *info); >> +void aarch64_cpu_register(const ARMCPUInfo *info); >> + >> +void register_cp_regs_for_features(ARMCPU *cpu); >> +void init_cpreg_list(ARMCPU *cpu); > > These can go to internals.h. OK, I'm squashing: -- >8 -- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad2f32efd5..2bd8aaff3d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1153,12 +1153,6 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - -void register_cp_regs_for_features(ARMCPU *cpu); -void init_cpreg_list(ARMCPU *cpu); - #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) #define ARM_AFF1_SHIFT 8 diff --git a/target/arm/internals.h b/target/arm/internals.h index 1dd9182a54..cfd64145ea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -182,6 +182,12 @@ static inline int r14_bank_number(int mode) return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); } +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); + +void register_cp_regs_for_features(ARMCPU *cpu); +void init_cpreg_list(ARMCPU *cpu); + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); --- > > Otherwise, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Thanks!
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index dfb9d5b827..35c3b0924e 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. @@ -63,29 +60,4 @@ struct AArch64CPUClass { ARMCPUClass parent_class; }; -void register_cp_regs_for_features(ARMCPU *cpu); -void init_cpreg_list(ARMCPU *cpu); - -/* Callback functions for the generic timer's timers. */ -void arm_gt_ptimer_cb(void *opaque); -void arm_gt_vtimer_cb(void *opaque); -void arm_gt_htimer_cb(void *opaque); -void arm_gt_stimer_cb(void *opaque); -void arm_gt_hvtimer_cb(void *opaque); - -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fb1b08371c..06f92dacb9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,11 +1116,39 @@ struct ArchCPU { uint64_t gt_cntfrq_hz; }; +/* Callback functions for the generic timer's timers. */ +void arm_gt_ptimer_cb(void *opaque); +void arm_gt_vtimer_cb(void *opaque); +void arm_gt_htimer_cb(void *opaque); +void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); + +void register_cp_regs_for_features(ARMCPU *cpu); +void init_cpreg_list(ARMCPU *cpu); + +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY
These definitions and declarations are only used by target/arm/, no need to expose them to generic hw/. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/arm/cpu-qom.h | 28 ---------------------------- target/arm/cpu.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 28 deletions(-)