| Message ID | 20231020111136.44401-4-philmd@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/i386/hvf: Style cleanup | expand |
On Fri, Oct 20, 2023 at 01:11:36PM +0200, Philippe Mathieu-Daudé wrote: > Date: Fri, 20 Oct 2023 13:11:36 +0200 > From: Philippe Mathieu-Daudé <philmd@linaro.org> > Subject: [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as > 'cpu' > X-Mailer: git-send-email 2.41.0 > > Follow the naming used by other files in target/i386/. > > No functional changes. > > Suggested-by: Zhao Liu <zhao1.liu@intel.com> > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/i386/hvf/x86_emu.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) Thanks! Reviewed-by: Zhao Liu <zhao1.liu@intel.com> > > diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c > index 5b82e84778..3a3f0a50d0 100644 > --- a/target/i386/hvf/x86_emu.c > +++ b/target/i386/hvf/x86_emu.c > @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) > > void simulate_rdmsr(CPUX86State *env) > { > - X86CPU *x86_cpu = env_archcpu(env); > + X86CPU *cpu = env_archcpu(env); > CPUState *cs = env_cpu(env); > uint32_t msr = ECX(env); > uint64_t val = 0; > @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env) > val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); > break; > case MSR_IA32_APICBASE: > - val = cpu_get_apic_base(x86_cpu->apic_state); > + val = cpu_get_apic_base(cpu->apic_state); > break; > case MSR_IA32_UCODE_REV: > - val = x86_cpu->ucode_rev; > + val = cpu->ucode_rev; > break; > case MSR_EFER: > val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); > @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) > > void simulate_wrmsr(CPUX86State *env) > { > - X86CPU *x86_cpu = env_archcpu(env); > + X86CPU *cpu = env_archcpu(env); > CPUState *cs = env_cpu(env); > uint32_t msr = ECX(env); > uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); > @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env) > case MSR_IA32_TSC: > break; > case MSR_IA32_APICBASE: > - cpu_set_apic_base(x86_cpu->apic_state, data); > + cpu_set_apic_base(cpu->apic_state, data); > break; > case MSR_FSBASE: > wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); > @@ -1419,8 +1419,8 @@ static void init_cmd_handler() > > void load_regs(CPUState *cs) > { > - X86CPU *x86_cpu = X86_CPU(cs); > - CPUX86State *env = &x86_cpu->env; > + X86CPU *cpu = X86_CPU(cs); > + CPUX86State *env = &cpu->env; > > int i = 0; > RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); > @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs) > > void store_regs(CPUState *cs) > { > - X86CPU *x86_cpu = X86_CPU(cs); > - CPUX86State *env = &x86_cpu->env; > + X86CPU *cpu = X86_CPU(cs); > + CPUX86State *env = &cpu->env; > > int i = 0; > wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); > -- > 2.41.0 >
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 5b82e84778..3a3f0a50d0 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env) val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(x86_cpu->apic_state); + val = cpu_get_apic_base(cpu->apic_state); break; case MSR_IA32_UCODE_REV: - val = x86_cpu->ucode_rev; + val = cpu->ucode_rev; break; case MSR_EFER: val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_cpu->apic_state, data); + cpu_set_apic_base(cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); @@ -1419,8 +1419,8 @@ static void init_cmd_handler() void load_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs) void store_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)