diff mbox series

[v2,34/35] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero

Message ID 20231028194522.245170-35-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg: Introduce TCG_COND_TST{EQ,NE} | expand

Commit Message

Richard Henderson Oct. 28, 2023, 7:45 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/translate.c | 49 +++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 26 deletions(-)

Comments

Philippe Mathieu-Daudé Nov. 8, 2023, 9:03 p.m. UTC | #1 
On 28/10/23 21:45, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/alpha/translate.c | 49 +++++++++++++++++++---------------------
>   1 file changed, 23 insertions(+), 26 deletions(-)
> 
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index c7daf46de7..c68c2bcd21 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -490,56 +490,53 @@ static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
>   
>   /* Fold -0.0 for comparison with COND.  */
>   
> -static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src)
> +static TCGv_i64 gen_fold_mzero(TCGCond *pcond, uint64_t *pimm, TCGv_i64 src)
>   {
> -    uint64_t mzero = 1ull << 63;
> +    TCGv_i64 tmp;
>   
> -    switch (cond) {
> +    *pimm = 0;
> +    switch (*pcond) {
>       case TCG_COND_LE:
>       case TCG_COND_GT:
>           /* For <= or >, the -0.0 value directly compares the way we want.  */
> -        tcg_gen_mov_i64(dest, src);
> -        break;
> +        return src;
>   
>       case TCG_COND_EQ:
>       case TCG_COND_NE:
> -        /* For == or !=, we can simply mask off the sign bit and compare.  */
> -        tcg_gen_andi_i64(dest, src, mzero - 1);
> -        break;
> +        /* For == or !=, we can compare without the sign bit. */

> +        *pcond = *pcond == TCG_COND_EQ ? TCG_COND_TSTEQ : TCG_COND_TSTNE;

OK, $subject is only this line, the rest is purely refactoring.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +        *pimm = INT64_MAX;
> +        return src;
>   
>       case TCG_COND_GE:
>       case TCG_COND_LT:
>           /* For >= or <, map -0.0 to +0.0. */
> -        tcg_gen_movcond_i64(TCG_COND_NE, dest, src, tcg_constant_i64(mzero),
> -                            src, tcg_constant_i64(0));
> -        break;
> +        tmp = tcg_temp_new_i64();
> +        tcg_gen_movcond_i64(TCG_COND_EQ, tmp,
> +                            src, tcg_constant_i64(INT64_MIN),
> +                            tcg_constant_i64(0), src);
> +        return tmp;
>   
>       default:
> -        abort();
> +        g_assert_not_reached();
>       }
>   }
diff mbox series

Patch

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index c7daf46de7..c68c2bcd21 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -490,56 +490,53 @@  static DisasJumpType gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
 
 /* Fold -0.0 for comparison with COND.  */
 
-static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src)
+static TCGv_i64 gen_fold_mzero(TCGCond *pcond, uint64_t *pimm, TCGv_i64 src)
 {
-    uint64_t mzero = 1ull << 63;
+    TCGv_i64 tmp;
 
-    switch (cond) {
+    *pimm = 0;
+    switch (*pcond) {
     case TCG_COND_LE:
     case TCG_COND_GT:
         /* For <= or >, the -0.0 value directly compares the way we want.  */
-        tcg_gen_mov_i64(dest, src);
-        break;
+        return src;
 
     case TCG_COND_EQ:
     case TCG_COND_NE:
-        /* For == or !=, we can simply mask off the sign bit and compare.  */
-        tcg_gen_andi_i64(dest, src, mzero - 1);
-        break;
+        /* For == or !=, we can compare without the sign bit. */
+        *pcond = *pcond == TCG_COND_EQ ? TCG_COND_TSTEQ : TCG_COND_TSTNE;
+        *pimm = INT64_MAX;
+        return src;
 
     case TCG_COND_GE:
     case TCG_COND_LT:
         /* For >= or <, map -0.0 to +0.0. */
-        tcg_gen_movcond_i64(TCG_COND_NE, dest, src, tcg_constant_i64(mzero),
-                            src, tcg_constant_i64(0));
-        break;
+        tmp = tcg_temp_new_i64();
+        tcg_gen_movcond_i64(TCG_COND_EQ, tmp,
+                            src, tcg_constant_i64(INT64_MIN),
+                            tcg_constant_i64(0), src);
+        return tmp;
 
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
 static DisasJumpType gen_fbcond(DisasContext *ctx, TCGCond cond, int ra,
                                 int32_t disp)
 {
-    TCGv cmp_tmp = tcg_temp_new();
-    DisasJumpType ret;
-
-    gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra));
-    ret = gen_bcond_internal(ctx, cond, cmp_tmp, 0, disp);
-    return ret;
+    uint64_t imm;
+    TCGv_i64 tmp = gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra));
+    return gen_bcond_internal(ctx, cond, tmp, imm, disp);
 }
 
 static void gen_fcmov(DisasContext *ctx, TCGCond cond, int ra, int rb, int rc)
 {
-    TCGv_i64 va, vb, z;
-
-    z = load_zero(ctx);
-    vb = load_fpr(ctx, rb);
-    va = tcg_temp_new();
-    gen_fold_mzero(cond, va, load_fpr(ctx, ra));
-
-    tcg_gen_movcond_i64(cond, dest_fpr(ctx, rc), va, z, vb, load_fpr(ctx, rc));
+    uint64_t imm;
+    TCGv_i64 tmp = gen_fold_mzero(&cond, &imm, load_fpr(ctx, ra));
+    tcg_gen_movcond_i64(cond, dest_fpr(ctx, rc),
+                        tmp, tcg_constant_i64(imm),
+                        load_fpr(ctx, rb), load_fpr(ctx, rc));
 }
 
 #define QUAL_RM_N       0x080   /* Round mode nearest even */