From patchwork Sun Aug 21 16:32:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 74382 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp1198385qga; Sun, 21 Aug 2016 09:33:20 -0700 (PDT) X-Received: by 10.28.182.136 with SMTP id g130mr11299735wmf.21.1471797200747; Sun, 21 Aug 2016 09:33:20 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id ei3si14770829wjd.49.2016.08.21.09.33.20; Sun, 21 Aug 2016 09:33:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B67B4B98B; Sun, 21 Aug 2016 18:33:19 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bhl-7MU8MqNq; Sun, 21 Aug 2016 18:33:19 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 33CF94B99D; Sun, 21 Aug 2016 18:33:19 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0611E4B99D for ; Sun, 21 Aug 2016 18:33:15 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T1AGW0mr-NhL for ; Sun, 21 Aug 2016 18:33:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conssluserg-03.nifty.com (conssluserg-03.nifty.com [210.131.2.82]) by theia.denx.de (Postfix) with ESMTPS id 4CAEF4B98B for ; Sun, 21 Aug 2016 18:33:09 +0200 (CEST) Received: from mail-yb0-f174.google.com (mail-yb0-f174.google.com [209.85.213.174]) (authenticated) by conssluserg-03.nifty.com with ESMTP id u7LGWrWR023841 for ; Mon, 22 Aug 2016 01:32:54 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conssluserg-03.nifty.com u7LGWrWR023841 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1471797174; bh=UChuEvrWD7+IiQs2XzHIANkd08XvpJmp99bdsfkVfgQ=; h=In-Reply-To:References:From:Date:Subject:To:Cc:From; b=KHsYb0ZegsCQrnuivJGQASeoRVQ01FSolraF5809JEk2ynDr1vGcuheNdAXyxNhuU BU1fTNRhV2cMcnI2NGHkhqWrlz/rkj9CVHuTix2Q88JVTTxqBjUQ/imCmKtuElZnXZ 9qAM7MHKYtd0OCYZKqT6oGZhRPILrJfh05J0vlwH6bI2DwUggb02Fw4WQKQNGkqRCd lNGKlCV5oev1eg1lXGsP1uHk0DswwwMqyMgeSj4c6RyBylMPj+zw6MQp4HMoy2fpY7 Y8tHbxCBzBmsIrQvhhKnVYTlOlviWvwn3y9rGft7A9SveoOjeCDQ13Yhkk9/9lmu2K xaJRoBilrMzZA== X-Nifty-SrcIP: [209.85.213.174] Received: by mail-yb0-f174.google.com with SMTP id a88so4249608ybi.0 for ; Sun, 21 Aug 2016 09:32:54 -0700 (PDT) X-Gm-Message-State: AEkoousqPJSNmsdSMTnmihdr/Y0GldV53dRE0A5rbCN16AqGpKAfhPh5cRg/CW7LBPprs269zFRr9VZ2GqZOsQ== X-Received: by 10.37.220.4 with SMTP id y4mr14028523ybe.150.1471797172978; Sun, 21 Aug 2016 09:32:52 -0700 (PDT) MIME-Version: 1.0 Received: by 10.37.224.71 with HTTP; Sun, 21 Aug 2016 09:32:52 -0700 (PDT) In-Reply-To: <20160821154324.GV5342@bill-the-cat> References: <1471786255-17712-1-git-send-email-trini@konsulko.com> <20160821154324.GV5342@bill-the-cat> From: Masahiro Yamada Date: Mon, 22 Aug 2016 01:32:52 +0900 X-Gmail-Original-Message-ID: Message-ID: To: Tom Rini Cc: U-Boot Mailing List Subject: Re: [U-Boot] [PATCH 1/1] ARM: Move SYS_CACHELINE_SIZE over to Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Hi Tom, 2016-08-22 0:43 GMT+09:00 Tom Rini : > On Mon, Aug 22, 2016 at 12:28:19AM +0900, Masahiro Yamada wrote: >> Hi Tom, >> >> >> >> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> > index aef901c..15cd66a 100644 >> > --- a/arch/arm/Kconfig >> > +++ b/arch/arm/Kconfig >> > @@ -79,6 +79,11 @@ config SYS_ARM_ARCH >> > default 4 if CPU_SA1100 >> > default 8 if ARM64 >> > >> > +config SYS_CACHELINE_SIZE >> > + int >> > + default 64 if CPU_V7 || ARM64 > > Note! I had a brain fart here last night and used 'printf %x' when I > thought I was doing 'printf %d', so, no, ARM64 should get moved up to > shift 7 / 128 bytes. As far as I know, the line size of the cores from ARM Ltd. (CA-53, 57, 72) is 64 byte. ARM64 Linux increased the line size up to 128 byte for the Cavium's core because it is multi-platform. ------------------------------>8-------------------------------------- commit 97303480753e48fb313dc0e15daaf11b0451cdb8 Author: Tirumalesh Chalamarla Date: Tue Sep 22 19:59:48 2015 +0200 arm64: Increase the max granular size Increase the standard cacheline size to avoid having locks in the same cacheline. Cavium's ThunderX core implements cache lines of 128 byte size. With current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could share the same cache line leading a performance degradation. Increasing the size fixes that. Increasing the size has no negative impact to cache invalidation on systems with a smaller cache line. There is an impact on memory usage, but that's not too important for arm64 use cases. Signed-off-by: Tirumalesh Chalamarla Signed-off-by: Robert Richter Acked-by: Timur Tabi Signed-off-by: Catalin Marinas --------------------------------------8<------------------------------------- U-Boot does not adopt multi-platform, so we can make the ARCH_THUNDERX select CACHESHIFT_7 and allow other ARM64 SoCs to stay at CACHESHIFT_6. Just my 2 cents. >> >> >> >> This idea was borrowed from Linux. >> (you can grep "_L1_CACHE_SHIFT" in Linux Kconfig files.) > > I'm agreeable to moving over to shift to more obviously align with the > Linux Kernel (and it will make other arches easier to migrate too). But > the UniPhier case currently looks to me like it's overloading what > CONFIG_SYS_CACHELINE_SIZE is doing, First, I'd like to know if CONFIG_SYS_CACHELINE_SIZE means the line size of L1 cache, or the largest line size across all the cache levels. > ie in the Linux Kernel it's not > setting the shift to 7, in 32bit. Or is this a 64bit only feature? > Thanks! CACHE_UNIPHIER is a full-custom outer cache only implemented in its 32bit SoC lineup. UniPhier (32bit) is a very unfortunate case where outer-cache has a different line size than the L1 line size. L1 (ARM native, inner): 32byte line (shift 5) L2 (UniPhier outer cache): 128byte line (shift 7) For Linux, it is just not upstreamed yet. If you are interested, check the following: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/400289.html If I set the shift to 7, it would affect all the other SoCs in multi_v7_defconfig, which other vendors would probably be unhappy about. Again, it is no problem in U-Boot, which is not multi-platform. -- Best Regards Masahiro Yamada _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index bde4499..5082b30 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -18,7 +18,7 @@ #include -#define L1_CACHE_SHIFT 6 +#define L1_CACHE_SHIFT 7 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /*