| Message ID | 20231120070910.16697-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/2] dt-bindings: PCI: qcom: adjust iommu-map for different SoC | expand |
> + minItems: 1
Hello Krzysztof,
the driver will accept 0 just fine, so I think this definition may be wrong.
I sent just generic "dt-bindings: PCI: qcom: delimit number of iommu-map entries" which doesn't care about the numbers (in similar fashion as other bindings having iommu-map).
Tell me what you think.
David
On Fri, Dec 29, 2023 at 04:36:31PM +0100, David wrote: > > + minItems: 1 > Hello Krzysztof, > > the driver will accept 0 just fine, so I think this definition may be wrong. > It's not entirely wrong but the actual SID mapping differs between SoCs. > I sent just generic "dt-bindings: PCI: qcom: delimit number of iommu-map entries" which doesn't care about the numbers (in similar fashion as other bindings having iommu-map). > No, we should not just ignore the MAX limit. If you add <N> number of entries exceeding the max SID assigned to PCIe bus, it will fail. - Mani > Tell me what you think. > > David >
On 29/12/2023 18:17, Manivannan Sadhasivam wrote: > On Fri, Dec 29, 2023 at 04:36:31PM +0100, David wrote: >>> + minItems: 1 >> Hello Krzysztof, >> >> the driver will accept 0 just fine, so I think this definition may be wrong. >> > It's not entirely wrong but the actual SID mapping differs between SoCs. Sure, I think I can live with this. > >> I sent just generic "dt-bindings: PCI: qcom: delimit number of iommu-map entries" which doesn't care about the numbers (in similar fashion as other bindings having iommu-map). >> > No, we should not just ignore the MAX limit. If you add <N> number of entries > exceeding the max SID assigned to PCIe bus, it will fail. > > - Mani Make sense, thanks for explanation. Reviewed-by: David Heidelberg <david@ixit.cz> >> Tell me what you think. >> >> David >>
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 8bfae8eb79a3..14d25e8a18e4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -62,7 +62,8 @@ properties: maxItems: 8 iommu-map: - maxItems: 2 + minItems: 1 + maxItems: 16 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later.
The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998 has one and SDM845 has sixteen, so allow wider number of items to fix dtbs_check warnings like: qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1], [512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes in v2: 1. Add Acs/Rb. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)