From patchwork Mon Mar 26 10:14:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 7462 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3106323E01 for ; Mon, 26 Mar 2012 10:14:43 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id CB1B8A18250 for ; Mon, 26 Mar 2012 10:14:42 +0000 (UTC) Received: by iage36 with SMTP id e36so10634895iag.11 for ; Mon, 26 Mar 2012 03:14:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:message-id :date:from:user-agent:mime-version:cc:subject:references:in-reply-to :x-originalarrivaltime:x-gm-message-state:content-type; bh=lermFqBpz08kFs3CV0AVAaJrFlageL2+saKG/d+/teI=; b=YoR9icQmiNOGXNM10Iwo8e/y/heYYNYIcfhWmplcF9coSmpUWF3EtIihcSvohHhsCt 0EHOvTmiGFi+p9fd7CGuqRNCWmHRTUKd4vd8Z4ADUqANw8ZLxhReIHPXL/UuQqO9ev57 SI8H7hZ0gFmQO4zJA1QScduw2ClonZCqnE+4PlxhMau8mE6LRrST4I30TtBuG0GdEMQg mobOvf5UVX3ulaTWTEaOZHzFOkg7ekKN3LamsahnoYjufv8/8RaeHfp7v7Qpv7psamFB +GqsSaho3fvgMxZGr9Tqm2i6ZPHBH63MPD/+zR0Uw021d0n+zZLg7tskJzbRUCoftS/I DSIw== Received: by 10.50.194.226 with SMTP id hz2mr5025472igc.44.1332756882285; Mon, 26 Mar 2012 03:14:42 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp14746ibw; Mon, 26 Mar 2012 03:14:41 -0700 (PDT) Received: by 10.68.225.70 with SMTP id ri6mr51624953pbc.88.1332756880537; Mon, 26 Mar 2012 03:14:40 -0700 (PDT) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id x8si17967436pbi.96.2012.03.26.03.14.40 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 26 Mar 2012 03:14:40 -0700 (PDT) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1SC6wh-00077F-8L from Andrew_Stubbs@mentor.com ; Mon, 26 Mar 2012 03:14:39 -0700 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Mon, 26 Mar 2012 03:14:38 -0700 Received: from [172.30.14.214] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Mon, 26 Mar 2012 11:14:36 +0100 Message-ID: <4F704189.4010302@codesourcery.com> Date: Mon, 26 Mar 2012 11:14:33 +0100 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120310 Thunderbird/11.0 MIME-Version: 1.0 CC: "gcc-patches@gcc.gnu.org" , "patches@linaro.org" Subject: Re: [PATCH][ARM] NEON DImode neg References: <4F4D12C5.9070805@codesourcery.com> In-Reply-To: <4F4D12C5.9070805@codesourcery.com> X-OriginalArrivalTime: 26 Mar 2012 10:14:38.0693 (UTC) FILETIME=[40823950:01CD0B39] X-Gm-Message-State: ALoCoQntLrZigbJ6EraoI7cRf/jkA5W+wY3k4i9T8lZCLv70WgmKyDmb+vwnry/AZJH5lZG7Tfc2 On 28/02/12 17:45, Andrew Stubbs wrote: > Hi all, > > This patch adds a DImode negate pattern for NEON. > > Unfortunately, the NEON vneg instruction only supports vectors, not > singletons, so there's no direct way to do it in DImode, and the > compiler ends up moving the value back to core registers, negating it, > and returning to NEON afterwards: > > fmrrd r2, r3, d16 @ int > negs r2, r2 > sbc r3, r3, r3, lsl #1 > fmdrr d16, r2, r3 @ int > > The new patch does it entirely in NEON: > > vmov.i32 d17, #0 @ di > vsub.i64 d16, d17, d16 > > (Note that this is the result when combined with my recent patch for > NEON DImode immediates. Without that you get a constant pool load.) This updates fixes a bootstrap failure caused by an early clobber error. I've also got a native regression test running now. OK? Andrew 2012-03-26 Andrew Stubbs gcc/ * config/arm/arm.md (negdi2): Use gen_negdi2_neon. * config/arm/neon.md (negdi2_neon): New insn. Also add splitters for core and NEON registers. --- gcc/config/arm/arm.md | 8 +++++++- gcc/config/arm/neon.md | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 751997f..f1dbbf7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4048,7 +4048,13 @@ (neg:DI (match_operand:DI 1 "s_register_operand" ""))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" - "" + { + if (TARGET_NEON) + { + emit_insn (gen_negdi2_neon (operands[0], operands[1])); + DONE; + } + } ) ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 3c88568..bf229a7 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -922,6 +922,43 @@ (const_string "neon_int_3")))] ) +(define_insn "negdi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "= w,?r,?&r,?w") + (neg:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w"))) + (clobber (match_scratch:DI 2 "=&w, X, X,&w")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON" + "#" + [(set_attr "length" "8") + (set_attr "arch" "nota8,*,*,onlya8")] +) + +; Split negdi2_neon for vfp registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_NEON && reload_completed && IS_VFP_REGNUM (REGNO (operands[0]))" + [(set (match_dup 2) (const_int 0)) + (parallel [(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + +; Split negdi2_neon for core registers +(define_split + [(set (match_operand:DI 0 "s_register_operand" "") + (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + (clobber (match_scratch:DI 2 "")) + (clobber (reg:CC CC_REGNUM))] + "TARGET_32BIT && reload_completed + && arm_general_register_operand (operands[0], DImode)" + [(parallel [(set (match_dup 0) (neg:DI (match_dup 1))) + (clobber (reg:CC CC_REGNUM))])] + "" +) + (define_insn "*umin3_neon" [(set (match_operand:VDQIW 0 "s_register_operand" "=w") (umin:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")