| Message ID | 20231213031646.28828-5-semen.protsenko@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm: exynos: Add E850-96 board | expand |
> -----Original Message----- > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sam Protsenko > Sent: Wednesday, December 13, 2023 12:17 PM > To: Minkyu Kang <mk7.kang@samsung.com>; Tom Rini <trini@konsulko.com>; > Lukasz Majewski <lukma@denx.de>; Sean Anderson <seanga2@gmail.com> > Cc: Simon Glass <sjg@chromium.org>; Heinrich Schuchardt > <xypron.glpk@gmx.de>; u-boot@lists.denx.de > Subject: [PATCH 04/13] soc: samsung: Add Exynos USI driver > > USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and > provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 > registers usually reside in the same register map as a particular > underlying protocol it implements, but have some particular offset. E.g. > on Exynos850 the USI_UART has 0x13820000 base address, where UART > registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc > offsets. Desired protocol can be chosen via SW_CONF register from System > Register block of the same domain as USI. > > Before starting to use a particular protocol, USIv2 must be configured > properly: > 1. Select protocol to be used via System Register > 2. Clear "reset" flag in USI_CON > 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be > disabled, so that the IP clock is not gated automatically); this is > done using USI_OPTION register > 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers > modification > > This driver implements the above behavior. Of course, USIv2 driver > should be probed before UART/I2C/SPI drivers. It can be achieved by > embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); > driver then walks underlying nodes and instantiates those. Driver also > handles USI configuration on PM resume, as register contents can be lost > during CPU suspend. > > This driver is designed with different USI versions in mind. So it > should be relatively easy to add new USI revisions to it later. > > Driver's code was copied over from Linux kernel [1] and adapted > correspondingly for U-Boot API. UCLASS_MISC is used, and although no > misc operations are implemented, it makes it easier to probe the driver > this way (as compared to UCLASS_NOP) and keep the code compact. > > [1] drivers/soc/samsung/exynos-usi.c > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Hi 2023년 12월 13일 (수) 12:42, Sam Protsenko <semen.protsenko@linaro.org>님이 작성: > USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and > provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 > registers usually reside in the same register map as a particular > underlying protocol it implements, but have some particular offset. E.g. > on Exynos850 the USI_UART has 0x13820000 base address, where UART > registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc > offsets. Desired protocol can be chosen via SW_CONF register from System > Register block of the same domain as USI. > > Before starting to use a particular protocol, USIv2 must be configured > properly: > 1. Select protocol to be used via System Register > 2. Clear "reset" flag in USI_CON > 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be > disabled, so that the IP clock is not gated automatically); this is > done using USI_OPTION register > 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers > modification > > This driver implements the above behavior. Of course, USIv2 driver > should be probed before UART/I2C/SPI drivers. It can be achieved by > embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); > driver then walks underlying nodes and instantiates those. Driver also > handles USI configuration on PM resume, as register contents can be lost > during CPU suspend. > > This driver is designed with different USI versions in mind. So it > should be relatively easy to add new USI revisions to it later. > > Driver's code was copied over from Linux kernel [1] and adapted > correspondingly for U-Boot API. UCLASS_MISC is used, and although no > misc operations are implemented, it makes it easier to probe the driver > this way (as compared to UCLASS_NOP) and keep the code compact. > > [1] drivers/soc/samsung/exynos-usi.c > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/samsung/Kconfig | 23 ++++ > drivers/soc/samsung/Makefile | 3 + > drivers/soc/samsung/exynos-usi.c | 218 +++++++++++++++++++++++++++++++ > 5 files changed, 246 insertions(+) > create mode 100644 drivers/soc/samsung/Kconfig > create mode 100644 drivers/soc/samsung/Makefile > create mode 100644 drivers/soc/samsung/exynos-usi.c > > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > index 85dac9de78a4..03433bc0e6d2 100644 > --- a/drivers/soc/Kconfig > +++ b/drivers/soc/Kconfig > @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET > This allows other drivers to verify the SoC familiy & revision > using > matching SoC attributes. > > +source "drivers/soc/samsung/Kconfig" > source "drivers/soc/ti/Kconfig" > > endmenu > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > index 84385650d46d..610bf816d40a 100644 > --- a/drivers/soc/Makefile > +++ b/drivers/soc/Makefile > @@ -2,6 +2,7 @@ > # > # Makefile for the U-Boot SOC specific device drivers. > > +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > obj-$(CONFIG_SOC_TI) += ti/ > obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o > obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o > diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig > new file mode 100644 > index 000000000000..ffb87fe79316 > --- /dev/null > +++ b/drivers/soc/samsung/Kconfig > @@ -0,0 +1,23 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +menuconfig SOC_SAMSUNG > + bool "Samsung SoC drivers support" > + > +if SOC_SAMSUNG > + > +config EXYNOS_USI > + bool "Exynos USI (Universal Serial Interface) driver" > + depends on ARCH_EXYNOS > + select MISC > + select REGMAP > + select SYSCON > + help > + Enable support for USI block. USI (Universal Serial Interface) > is an > + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and > + ExynosAutoV9. USI block can be configured to provide one of the > + following serial protocols: UART, SPI or High Speed I2C. > + > + This driver allows one to configure USI for desired protocol, > which > + is usually done in USI node in Device Tree. > + > +endif > diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile > new file mode 100644 > index 000000000000..833ac073fbfa > --- /dev/null > +++ b/drivers/soc/samsung/Makefile > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o > diff --git a/drivers/soc/samsung/exynos-usi.c > b/drivers/soc/samsung/exynos-usi.c > new file mode 100644 > index 000000000000..23255177e6e3 > --- /dev/null > +++ b/drivers/soc/samsung/exynos-usi.c > @@ -0,0 +1,218 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Linaro Ltd. > + * Author: Sam Protsenko <semen.protsenko@linaro.org> > + * > + * Samsung Exynos USI driver (Universal Serial Interface). > + */ > + > +#include <dm.h> > +#include <dm/device_compat.h> > +#include <errno.h> > +#include <regmap.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <linux/bitops.h> > +#include <linux/delay.h> > +#include <linux/err.h> > + > +#include <dt-bindings/soc/samsung,exynos-usi.h> > + > +/* USIv2: System Register: SW_CONF register bits */ > +#define USI_V2_SW_CONF_NONE 0x0 > +#define USI_V2_SW_CONF_UART BIT(0) > +#define USI_V2_SW_CONF_SPI BIT(1) > +#define USI_V2_SW_CONF_I2C BIT(2) > +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI > | \ > + USI_V2_SW_CONF_I2C) > + > +/* USIv2: USI register offsets */ > +#define USI_CON 0x04 > +#define USI_OPTION 0x08 > + > +/* USIv2: USI register bits */ > +#define USI_CON_RESET BIT(0) > +#define USI_OPTION_CLKREQ_ON BIT(1) > +#define USI_OPTION_CLKSTOP_ON BIT(2) > + > +enum exynos_usi_ver { > + USI_VER2 = 2, > +}; > + > +struct exynos_usi_variant { > + enum exynos_usi_ver ver; /* USI IP-core version */ > + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols > */ > + size_t min_mode; /* first index in > exynos_usi_modes[] */ > + size_t max_mode; /* last index in > exynos_usi_modes[] */ > +}; > + > +struct exynos_usi { > + struct udevice *dev; > + void __iomem *regs; /* USI register map */ > + > + size_t mode; /* current USI SW_CONF mode index > */ > + bool clkreq_on; /* always provide clock to IP */ > + > + /* System Register */ > + struct regmap *sysreg; /* System Register map */ > + unsigned int sw_conf; /* SW_CONF register offset in > sysreg */ > + > + const struct exynos_usi_variant *data; > +}; > + > +struct exynos_usi_mode { > + const char *name; /* mode name */ > + unsigned int val; /* mode register value */ > +}; > + > +static const struct exynos_usi_mode exynos_usi_modes[] = { > + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, > + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, > + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, > + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, > +}; > + > +static const struct exynos_usi_variant exynos850_usi_data = { > + .ver = USI_VER2, > + .sw_conf_mask = USI_V2_SW_CONF_MASK, > + .min_mode = USI_V2_NONE, > + .max_mode = USI_V2_I2C, > +}; > + > +static const struct udevice_id exynos_usi_ids[] = { > + { > + .compatible = "samsung,exynos850-usi", > + .data = (ulong)&exynos850_usi_data, > + }, > + { } /* sentinel */ > +}; > + > +/** > + * exynos_usi_set_sw_conf - Set USI block configuration mode > + * @usi: USI driver object > + * @mode: Mode index > + * > + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. > + * > + * Return: 0 on success, or negative error code on failure. > + */ > +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) The value of mode is same as usi->mode, but is there a reason to pass it as a parameter? > +{ > + unsigned int val; > + int ret; > + > + if (mode < usi->data->min_mode || mode > usi->data->max_mode) > + return -EINVAL; > + > + val = exynos_usi_modes[mode].val; > + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, > + usi->data->sw_conf_mask, val); > + if (ret) > + return ret; > + > + usi->mode = mode; This will obviously be the same value always. > + dev_dbg(usi->dev, "protocol: %s\n", > exynos_usi_modes[usi->mode].name); > + > + return 0; > +} > + > +/** > + * exynos_usi_enable - Initialize USI block > + * @usi: USI driver object > + * > + * USI IP-core start state is "reset" (on startup and after CPU resume). > This > + * routine enables the USI block by clearing the reset flag. It also > configures > + * HWACG behavior (needed e.g. for UART Rx). It should be performed before > + * underlying protocol becomes functional. > + */ > +static void exynos_usi_enable(const struct exynos_usi *usi) > +{ > + u32 val; > + > + /* Enable USI block */ > + val = readl(usi->regs + USI_CON); > + val &= ~USI_CON_RESET; > + writel(val, usi->regs + USI_CON); > + udelay(1); > + > + /* Continuously provide the clock to USI IP w/o gating */ > + if (usi->clkreq_on) { > + val = readl(usi->regs + USI_OPTION); > + val &= ~USI_OPTION_CLKSTOP_ON; > + val |= USI_OPTION_CLKREQ_ON; > + writel(val, usi->regs + USI_OPTION); > + } > +} > + > +static int exynos_usi_configure(struct exynos_usi *usi) > +{ > + int ret; > + > + ret = exynos_usi_set_sw_conf(usi, usi->mode); > + if (ret) > + return ret; > + > + if (usi->data->ver == USI_VER2) > + exynos_usi_enable(usi); > + > + return 0; > +} > + > +static int exynos_usi_parse_dt(struct exynos_usi *usi) > +{ > + struct udevice *dev = usi->dev; > + ofnode node; > + int ret; > + u32 mode; > + > + node = dev_ofnode(dev); > + > + ret = ofnode_read_u32(node, "samsung,mode", &mode); > + if (ret) > + return ret; > + if (mode < usi->data->min_mode || mode > usi->data->max_mode) > + return -EINVAL; > + usi->mode = mode; > + > + usi->sysreg = syscon_regmap_lookup_by_phandle(dev, > "samsung,sysreg"); > + if (IS_ERR(usi->sysreg)) > + return PTR_ERR(usi->sysreg); > + > + ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, > &usi->sw_conf); > + if (ret) > + return ret; > + > + usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on"); > + > + return 0; > +} > + > +static int exynos_usi_probe(struct udevice *dev) > +{ > + struct exynos_usi *usi; > + int ret; > + > + usi = dev_get_priv(dev); > + usi->dev = dev; > + usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev); > + > + ret = exynos_usi_parse_dt(usi); > + if (ret) > + return ret; > + > + if (usi->data->ver == USI_VER2) { > + usi->regs = dev_read_addr_ptr(dev); > + if (!usi->regs) > + return -ENODEV; > + } > + > + return exynos_usi_configure(usi); > +} > + > +U_BOOT_DRIVER(exynos_usi) = { > + .name = "exynos-usi", > + .id = UCLASS_MISC, > + .of_match = exynos_usi_ids, > + .probe = exynos_usi_probe, > + .priv_auto = sizeof(struct exynos_usi), > +}; > -- > 2.39.2 > Thanks. Minkyu Kang.
Hi Sam, On Wed, Dec 13, 2023 at 3:16 AM Sam Protsenko <semen.protsenko@linaro.org> wrote: > > USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and > provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 > registers usually reside in the same register map as a particular > underlying protocol it implements, but have some particular offset. E.g. > on Exynos850 the USI_UART has 0x13820000 base address, where UART > registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc > offsets. Desired protocol can be chosen via SW_CONF register from System > Register block of the same domain as USI. > > Before starting to use a particular protocol, USIv2 must be configured > properly: > 1. Select protocol to be used via System Register > 2. Clear "reset" flag in USI_CON > 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be > disabled, so that the IP clock is not gated automatically); this is > done using USI_OPTION register > 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers > modification > > This driver implements the above behavior. Of course, USIv2 driver > should be probed before UART/I2C/SPI drivers. It can be achieved by > embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); > driver then walks underlying nodes and instantiates those. Driver also > handles USI configuration on PM resume, as register contents can be lost > during CPU suspend. > > This driver is designed with different USI versions in mind. So it > should be relatively easy to add new USI revisions to it later. > > Driver's code was copied over from Linux kernel [1] and adapted > correspondingly for U-Boot API. UCLASS_MISC is used, and although no > misc operations are implemented, it makes it easier to probe the driver > this way (as compared to UCLASS_NOP) and keep the code compact. > > [1] drivers/soc/samsung/exynos-usi.c > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > drivers/soc/Kconfig | 1 + > drivers/soc/Makefile | 1 + > drivers/soc/samsung/Kconfig | 23 ++++ > drivers/soc/samsung/Makefile | 3 + > drivers/soc/samsung/exynos-usi.c | 218 +++++++++++++++++++++++++++++++ > 5 files changed, 246 insertions(+) > create mode 100644 drivers/soc/samsung/Kconfig > create mode 100644 drivers/soc/samsung/Makefile > create mode 100644 drivers/soc/samsung/exynos-usi.c > Just a few nits here Reviewed-by: Simon Glass <sjg@chromium.org> > diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig > index 85dac9de78a4..03433bc0e6d2 100644 > --- a/drivers/soc/Kconfig > +++ b/drivers/soc/Kconfig > @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET > This allows other drivers to verify the SoC familiy & revision using > matching SoC attributes. > > +source "drivers/soc/samsung/Kconfig" > source "drivers/soc/ti/Kconfig" > > endmenu > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile > index 84385650d46d..610bf816d40a 100644 > --- a/drivers/soc/Makefile > +++ b/drivers/soc/Makefile > @@ -2,6 +2,7 @@ > # > # Makefile for the U-Boot SOC specific device drivers. > > +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ > obj-$(CONFIG_SOC_TI) += ti/ > obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o > obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o > diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig > new file mode 100644 > index 000000000000..ffb87fe79316 > --- /dev/null > +++ b/drivers/soc/samsung/Kconfig > @@ -0,0 +1,23 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +menuconfig SOC_SAMSUNG > + bool "Samsung SoC drivers support" > + > +if SOC_SAMSUNG > + > +config EXYNOS_USI > + bool "Exynos USI (Universal Serial Interface) driver" > + depends on ARCH_EXYNOS > + select MISC > + select REGMAP > + select SYSCON > + help > + Enable support for USI block. USI (Universal Serial Interface) is an > + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and > + ExynosAutoV9. USI block can be configured to provide one of the > + following serial protocols: UART, SPI or High Speed I2C. > + > + This driver allows one to configure USI for desired protocol, which > + is usually done in USI node in Device Tree. > + > +endif > diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile > new file mode 100644 > index 000000000000..833ac073fbfa > --- /dev/null > +++ b/drivers/soc/samsung/Makefile > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o > diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c > new file mode 100644 > index 000000000000..23255177e6e3 > --- /dev/null > +++ b/drivers/soc/samsung/exynos-usi.c > @@ -0,0 +1,218 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Linaro Ltd. > + * Author: Sam Protsenko <semen.protsenko@linaro.org> > + * > + * Samsung Exynos USI driver (Universal Serial Interface). > + */ > + > +#include <dm.h> > +#include <dm/device_compat.h> > +#include <errno.h> > +#include <regmap.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <linux/bitops.h> > +#include <linux/delay.h> > +#include <linux/err.h> > + > +#include <dt-bindings/soc/samsung,exynos-usi.h> > + > +/* USIv2: System Register: SW_CONF register bits */ > +#define USI_V2_SW_CONF_NONE 0x0 > +#define USI_V2_SW_CONF_UART BIT(0) > +#define USI_V2_SW_CONF_SPI BIT(1) > +#define USI_V2_SW_CONF_I2C BIT(2) > +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \ > + USI_V2_SW_CONF_I2C) > + > +/* USIv2: USI register offsets */ > +#define USI_CON 0x04 > +#define USI_OPTION 0x08 > + > +/* USIv2: USI register bits */ > +#define USI_CON_RESET BIT(0) > +#define USI_OPTION_CLKREQ_ON BIT(1) > +#define USI_OPTION_CLKSTOP_ON BIT(2) > + > +enum exynos_usi_ver { > + USI_VER2 = 2, > +}; > + > +struct exynos_usi_variant { > + enum exynos_usi_ver ver; /* USI IP-core version */ > + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */ > + size_t min_mode; /* first index in exynos_usi_modes[] */ > + size_t max_mode; /* last index in exynos_usi_modes[] */ > +}; > + > +struct exynos_usi { > + struct udevice *dev; Can we drop this? It doesn't seem very useful and we try to avoid having bidirectional pointers. since it is possible to get the 'priv' pointer from the device. > + void __iomem *regs; /* USI register map */ > + > + size_t mode; /* current USI SW_CONF mode index */ > + bool clkreq_on; /* always provide clock to IP */ > + > + /* System Register */ > + struct regmap *sysreg; /* System Register map */ > + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ > + > + const struct exynos_usi_variant *data; > +}; > + > +struct exynos_usi_mode { > + const char *name; /* mode name */ > + unsigned int val; /* mode register value */ > +}; > + > +static const struct exynos_usi_mode exynos_usi_modes[] = { > + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, > + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, > + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, > + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, > +}; > + > +static const struct exynos_usi_variant exynos850_usi_data = { > + .ver = USI_VER2, > + .sw_conf_mask = USI_V2_SW_CONF_MASK, > + .min_mode = USI_V2_NONE, > + .max_mode = USI_V2_I2C, > +}; > + > +static const struct udevice_id exynos_usi_ids[] = { > + { > + .compatible = "samsung,exynos850-usi", > + .data = (ulong)&exynos850_usi_data, > + }, > + { } /* sentinel */ > +}; > + > +/** > + * exynos_usi_set_sw_conf - Set USI block configuration mode > + * @usi: USI driver object > + * @mode: Mode index > + * > + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. > + * > + * Return: 0 on success, or negative error code on failure. > + */ > +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) > +{ > + unsigned int val; > + int ret; > + > + if (mode < usi->data->min_mode || mode > usi->data->max_mode) > + return -EINVAL; > + > + val = exynos_usi_modes[mode].val; > + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, > + usi->data->sw_conf_mask, val); > + if (ret) > + return ret; > + > + usi->mode = mode; > + dev_dbg(usi->dev, "protocol: %s\n", exynos_usi_modes[usi->mode].name); > + > + return 0; > +} > + > +/** > + * exynos_usi_enable - Initialize USI block > + * @usi: USI driver object > + * > + * USI IP-core start state is "reset" (on startup and after CPU resume). This > + * routine enables the USI block by clearing the reset flag. It also configures > + * HWACG behavior (needed e.g. for UART Rx). It should be performed before > + * underlying protocol becomes functional. > + */ > +static void exynos_usi_enable(const struct exynos_usi *usi) > +{ > + u32 val; > + > + /* Enable USI block */ > + val = readl(usi->regs + USI_CON); > + val &= ~USI_CON_RESET; > + writel(val, usi->regs + USI_CON); > + udelay(1); > + > + /* Continuously provide the clock to USI IP w/o gating */ > + if (usi->clkreq_on) { > + val = readl(usi->regs + USI_OPTION); > + val &= ~USI_OPTION_CLKSTOP_ON; > + val |= USI_OPTION_CLKREQ_ON; > + writel(val, usi->regs + USI_OPTION); > + } > +} > + > +static int exynos_usi_configure(struct exynos_usi *usi) > +{ > + int ret; > + > + ret = exynos_usi_set_sw_conf(usi, usi->mode); > + if (ret) > + return ret; > + > + if (usi->data->ver == USI_VER2) > + exynos_usi_enable(usi); > + > + return 0; > +} > + > +static int exynos_usi_parse_dt(struct exynos_usi *usi) Use of_to_plat() method? > +{ > + struct udevice *dev = usi->dev; > + ofnode node; > + int ret; > + u32 mode; > + > + node = dev_ofnode(dev); > + > + ret = ofnode_read_u32(node, "samsung,mode", &mode); > + if (ret) > + return ret; > + if (mode < usi->data->min_mode || mode > usi->data->max_mode) > + return -EINVAL; > + usi->mode = mode; > + > + usi->sysreg = syscon_regmap_lookup_by_phandle(dev, "samsung,sysreg"); > + if (IS_ERR(usi->sysreg)) > + return PTR_ERR(usi->sysreg); > + > + ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, &usi->sw_conf); > + if (ret) > + return ret; > + > + usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on"); > + > + return 0; > +} > + > +static int exynos_usi_probe(struct udevice *dev) > +{ > + struct exynos_usi *usi; > + int ret; > + > + usi = dev_get_priv(dev); > + usi->dev = dev; Hoping you can drop that > + usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev); > + > + ret = exynos_usi_parse_dt(usi); > + if (ret) > + return ret; > + > + if (usi->data->ver == USI_VER2) { > + usi->regs = dev_read_addr_ptr(dev); > + if (!usi->regs) > + return -ENODEV; > + } > + > + return exynos_usi_configure(usi); > +} > + > +U_BOOT_DRIVER(exynos_usi) = { > + .name = "exynos-usi", > + .id = UCLASS_MISC, > + .of_match = exynos_usi_ids, > + .probe = exynos_usi_probe, > + .priv_auto = sizeof(struct exynos_usi), > +}; > -- > 2.39.2 > Regards, Simon
On Wed, Dec 27, 2023 at 3:11 AM Minkyu Kang <promsoft@gmail.com> wrote: > > Hi > > > 2023년 12월 13일 (수) 12:42, Sam Protsenko <semen.protsenko@linaro.org>님이 작성: >> [snip] >> + >> +/** >> + * exynos_usi_set_sw_conf - Set USI block configuration mode >> + * @usi: USI driver object >> + * @mode: Mode index >> + * >> + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. >> + * >> + * Return: 0 on success, or negative error code on failure. >> + */ >> +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) > > > The value of mode is same as usi->mode, but is there a reason to pass it as a parameter? > >> >> +{ >> + unsigned int val; >> + int ret; >> + >> + if (mode < usi->data->min_mode || mode > usi->data->max_mode) >> + return -EINVAL; >> + >> + val = exynos_usi_modes[mode].val; >> + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, >> + usi->data->sw_conf_mask, val); >> + if (ret) >> + return ret; >> + >> + usi->mode = mode; > > > This will obviously be the same value always. > Thanks for the review! Yes, you are right. This code was copy-pasted from Linux kernel. So at the time I thought it was better to leave it as is, for backporting reasons. But now that I look at it, this won't be too helpful. So I'll get rid of it in v2. [snip]
On Wed, Dec 27, 2023 at 11:49 AM Simon Glass <sjg@chromium.org> wrote: > > Hi Sam, > [snip] > > Just a few nits here > > Reviewed-by: Simon Glass <sjg@chromium.org> > [snip] > > + > > +struct exynos_usi { > > + struct udevice *dev; > > Can we drop this? It doesn't seem very useful and we try to avoid > having bidirectional pointers. since it is possible to get the 'priv' > pointer from the device. > Sure. I tried to keep the driver as close as possible to Linux kernel's version, where I borrowed it from. But if it's the current preference in U-Boot, I'll fix this in v2. [snip] > > +static int exynos_usi_parse_dt(struct exynos_usi *usi) > > Use of_to_plat() method? > Will do in v2. Thanks for the review! [snip]
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 85dac9de78a4..03433bc0e6d2 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +source "drivers/soc/samsung/Kconfig" source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 84385650d46d..610bf816d40a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index 000000000000..ffb87fe79316 --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_SAMSUNG + bool "Samsung SoC drivers support" + +if SOC_SAMSUNG + +config EXYNOS_USI + bool "Exynos USI (Universal Serial Interface) driver" + depends on ARCH_EXYNOS + select MISC + select REGMAP + select SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV9. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + +endif diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index 000000000000..833ac073fbfa --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index 000000000000..23255177e6e3 --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <errno.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> + +#include <dt-bindings/soc/samsung,exynos-usi.h> + +/* USIv2: System Register: SW_CONF register bits */ +#define USI_V2_SW_CONF_NONE 0x0 +#define USI_V2_SW_CONF_UART BIT(0) +#define USI_V2_SW_CONF_SPI BIT(1) +#define USI_V2_SW_CONF_I2C BIT(2) +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \ + USI_V2_SW_CONF_I2C) + +/* USIv2: USI register offsets */ +#define USI_CON 0x04 +#define USI_OPTION 0x08 + +/* USIv2: USI register bits */ +#define USI_CON_RESET BIT(0) +#define USI_OPTION_CLKREQ_ON BIT(1) +#define USI_OPTION_CLKSTOP_ON BIT(2) + +enum exynos_usi_ver { + USI_VER2 = 2, +}; + +struct exynos_usi_variant { + enum exynos_usi_ver ver; /* USI IP-core version */ + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */ + size_t min_mode; /* first index in exynos_usi_modes[] */ + size_t max_mode; /* last index in exynos_usi_modes[] */ +}; + +struct exynos_usi { + struct udevice *dev; + void __iomem *regs; /* USI register map */ + + size_t mode; /* current USI SW_CONF mode index */ + bool clkreq_on; /* always provide clock to IP */ + + /* System Register */ + struct regmap *sysreg; /* System Register map */ + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ + + const struct exynos_usi_variant *data; +}; + +struct exynos_usi_mode { + const char *name; /* mode name */ + unsigned int val; /* mode register value */ +}; + +static const struct exynos_usi_mode exynos_usi_modes[] = { + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, +}; + +static const struct exynos_usi_variant exynos850_usi_data = { + .ver = USI_VER2, + .sw_conf_mask = USI_V2_SW_CONF_MASK, + .min_mode = USI_V2_NONE, + .max_mode = USI_V2_I2C, +}; + +static const struct udevice_id exynos_usi_ids[] = { + { + .compatible = "samsung,exynos850-usi", + .data = (ulong)&exynos850_usi_data, + }, + { } /* sentinel */ +}; + +/** + * exynos_usi_set_sw_conf - Set USI block configuration mode + * @usi: USI driver object + * @mode: Mode index + * + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core. + * + * Return: 0 on success, or negative error code on failure. + */ +static int exynos_usi_set_sw_conf(struct exynos_usi *usi, size_t mode) +{ + unsigned int val; + int ret; + + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + + val = exynos_usi_modes[mode].val; + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, + usi->data->sw_conf_mask, val); + if (ret) + return ret; + + usi->mode = mode; + dev_dbg(usi->dev, "protocol: %s\n", exynos_usi_modes[usi->mode].name); + + return 0; +} + +/** + * exynos_usi_enable - Initialize USI block + * @usi: USI driver object + * + * USI IP-core start state is "reset" (on startup and after CPU resume). This + * routine enables the USI block by clearing the reset flag. It also configures + * HWACG behavior (needed e.g. for UART Rx). It should be performed before + * underlying protocol becomes functional. + */ +static void exynos_usi_enable(const struct exynos_usi *usi) +{ + u32 val; + + /* Enable USI block */ + val = readl(usi->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, usi->regs + USI_CON); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating */ + if (usi->clkreq_on) { + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKSTOP_ON; + val |= USI_OPTION_CLKREQ_ON; + writel(val, usi->regs + USI_OPTION); + } +} + +static int exynos_usi_configure(struct exynos_usi *usi) +{ + int ret; + + ret = exynos_usi_set_sw_conf(usi, usi->mode); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) + exynos_usi_enable(usi); + + return 0; +} + +static int exynos_usi_parse_dt(struct exynos_usi *usi) +{ + struct udevice *dev = usi->dev; + ofnode node; + int ret; + u32 mode; + + node = dev_ofnode(dev); + + ret = ofnode_read_u32(node, "samsung,mode", &mode); + if (ret) + return ret; + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + usi->mode = mode; + + usi->sysreg = syscon_regmap_lookup_by_phandle(dev, "samsung,sysreg"); + if (IS_ERR(usi->sysreg)) + return PTR_ERR(usi->sysreg); + + ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, &usi->sw_conf); + if (ret) + return ret; + + usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on"); + + return 0; +} + +static int exynos_usi_probe(struct udevice *dev) +{ + struct exynos_usi *usi; + int ret; + + usi = dev_get_priv(dev); + usi->dev = dev; + usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev); + + ret = exynos_usi_parse_dt(usi); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) { + usi->regs = dev_read_addr_ptr(dev); + if (!usi->regs) + return -ENODEV; + } + + return exynos_usi_configure(usi); +} + +U_BOOT_DRIVER(exynos_usi) = { + .name = "exynos-usi", + .id = UCLASS_MISC, + .of_match = exynos_usi_ids, + .probe = exynos_usi_probe, + .priv_auto = sizeof(struct exynos_usi), +};
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Driver's code was copied over from Linux kernel [1] and adapted correspondingly for U-Boot API. UCLASS_MISC is used, and although no misc operations are implemented, it makes it easier to probe the driver this way (as compared to UCLASS_NOP) and keep the code compact. [1] drivers/soc/samsung/exynos-usi.c Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/samsung/Kconfig | 23 ++++ drivers/soc/samsung/Makefile | 3 + drivers/soc/samsung/exynos-usi.c | 218 +++++++++++++++++++++++++++++++ 5 files changed, 246 insertions(+) create mode 100644 drivers/soc/samsung/Kconfig create mode 100644 drivers/soc/samsung/Makefile create mode 100644 drivers/soc/samsung/exynos-usi.c