@@ -854,9 +854,30 @@ static const uuid_t dram_event_uuid = CXL_EVENT_DRAM_UUID;
*/
static const uuid_t mem_mod_event_uuid = CXL_EVENT_MEM_MODULE_UUID;
-static void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
- enum cxl_event_log_type type,
- struct cxl_event_record_raw *record)
+void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
+ enum cxl_event_log_type type,
+ enum cxl_event_type event_type,
+ union cxl_event *event)
+{
+ switch (event_type) {
+ case CXL_CPER_EVENT_GEN_MEDIA:
+ trace_cxl_general_media(cxlmd, type, &gen_media_event_uuid,
+ &event->gen_media);
+ break;
+ case CXL_CPER_EVENT_DRAM:
+ trace_cxl_dram(cxlmd, type, &dram_event_uuid, &event->dram);
+ break;
+ case CXL_CPER_EVENT_MEM_MODULE:
+ trace_cxl_memory_module(cxlmd, type, &mem_mod_event_uuid,
+ &event->mem_module);
+ break;
+ }
+}
+EXPORT_SYMBOL_NS_GPL(cxl_event_trace_record, CXL);
+
+static void __cxl_event_trace_record(const struct cxl_memdev *cxlmd,
+ enum cxl_event_log_type type,
+ struct cxl_event_record_raw *record)
{
union cxl_event *evt = &record->event;
uuid_t *id = &record->id;
@@ -979,8 +1000,8 @@ static void cxl_mem_get_records_log(struct cxl_memdev_state *mds,
break;
for (i = 0; i < nr_rec; i++)
- cxl_event_trace_record(cxlmd, type,
- &payload->records[i]);
+ __cxl_event_trace_record(cxlmd, type,
+ &payload->records[i]);
if (payload->flags & CXL_GET_EVENT_FLAG_OVERFLOW)
trace_cxl_overflow(cxlmd, type, payload);
@@ -481,6 +481,8 @@ struct cxl_memdev_state {
struct cxl_security_state security;
struct cxl_fw_state fw;
+ struct notifier_block cxl_cper_nb;
+
struct rcuwait mbox_wait;
int (*mbox_send)(struct cxl_memdev_state *mds,
struct cxl_mbox_cmd *cmd);
@@ -802,6 +804,10 @@ void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
unsigned long *cmds);
void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
+void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
+ enum cxl_event_log_type type,
+ enum cxl_event_type event_type,
+ union cxl_event *event);
int cxl_set_timestamp(struct cxl_memdev_state *mds);
int cxl_poison_state_init(struct cxl_memdev_state *mds);
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
+#include <asm-generic/unaligned.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/moduleparam.h>
#include <linux/module.h>
@@ -969,6 +970,55 @@ static struct pci_driver cxl_pci_driver = {
},
};
+#define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0)
+static void cxl_cper_event_call(struct cxl_cper_event_data *ev_data)
+{
+ struct cper_cxl_event_devid *device_id = &ev_data->rec->hdr.device_id;
+ struct cxl_dev_state *cxlds = NULL;
+ enum cxl_event_log_type log_type;
+ struct pci_dev *pdev;
+ unsigned int devfn;
+ u32 hdr_flags;
+
+ devfn = PCI_DEVFN(device_id->device_num, device_id->func_num);
+ pdev = pci_get_domain_bus_and_slot(device_id->segment_num,
+ device_id->bus_num, devfn);
+
+ guard(mutex)(&pdev->dev.mutex);
+ if (pdev->driver == &cxl_pci_driver)
+ cxlds = pci_get_drvdata(pdev);
+ if (!cxlds)
+ goto out;
+
+ /* Fabricate a log type */
+ hdr_flags = get_unaligned_le24(ev_data->rec->event.generic.hdr.flags);
+ log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags);
+
+ cxl_event_trace_record(cxlds->cxlmd, log_type, ev_data->event_type,
+ &ev_data->rec->event);
+out:
+ pci_dev_put(pdev);
+}
+
+static int __init cxl_pci_driver_init(void)
+{
+ int rc;
+
+ rc = pci_register_driver(&cxl_pci_driver);
+ if (rc)
+ return rc;
+
+ cxl_cper_register_notifier(cxl_cper_event_call);
+ return 0;
+}
+
+static void __exit cxl_pci_driver_exit(void)
+{
+ cxl_cper_unregister_notifier();
+ pci_unregister_driver(&cxl_pci_driver);
+}
+
+module_init(cxl_pci_driver_init);
+module_exit(cxl_pci_driver_exit);
MODULE_LICENSE("GPL v2");
-module_pci_driver(cxl_pci_driver);
MODULE_IMPORT_NS(CXL);
If the firmware has configured CXL event support to be firmware first the OS can process those events through CPER records. The CXL layer has unique DPA to HPA knowledge and standard event trace parsing in place. CPER records contain Bus, Device, Function information which can be used to identify the PCI device which is sending the event. Change pci driver registration to include registration for a CXL CPER callback to process the events through the trace subsystem. Signed-off-by: Ira Weiny <ira.weiny@intel.com> --- Changes from v1: [djbw: use single registration function] --- drivers/cxl/core/mbox.c | 31 ++++++++++++++++++++++++----- drivers/cxl/cxlmem.h | 6 ++++++ drivers/cxl/pci.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 83 insertions(+), 6 deletions(-)