diff mbox series

[1/2] clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config

Message ID 20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org
State Accepted
Commit 3f8d7f490a33625786b427ec925215c4c1f191d1
Headers show
Series 8650 PLL config updates | expand

Commit Message

Konrad Dybcio Dec. 19, 2023, 6:55 p.m. UTC 
These values were missing. Add them.

Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/clk/qcom/gpucc-sm8650.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c
index 5ae494e17ee4..03307e482aca 100644
--- a/drivers/clk/qcom/gpucc-sm8650.c
+++ b/drivers/clk/qcom/gpucc-sm8650.c
@@ -50,6 +50,7 @@  static const struct alpha_pll_config gpu_cc_pll0_config = {
 	.test_ctl_val = 0x00000000,
 	.test_ctl_hi_val = 0x00000003,
 	.test_ctl_hi1_val = 0x00009000,
+	.test_ctl_hi2_val = 0x00000034,
 	.user_ctl_val = 0x00000000,
 	.user_ctl_hi_val = 0x00000005,
 };
@@ -80,6 +81,7 @@  static const struct alpha_pll_config gpu_cc_pll1_config = {
 	.test_ctl_val = 0x00000000,
 	.test_ctl_hi_val = 0x00000003,
 	.test_ctl_hi1_val = 0x00009000,
+	.test_ctl_hi2_val = 0x00000034,
 	.user_ctl_val = 0x00000000,
 	.user_ctl_hi_val = 0x00000005,
 };