From patchwork Wed Sep 7 16:26:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 75686 Delivered-To: patch@linaro.org Received: by 10.140.106.11 with SMTP id d11csp409538qgf; Wed, 7 Sep 2016 09:27:09 -0700 (PDT) X-Received: by 10.66.9.42 with SMTP id w10mr84535716paa.34.1473265629688; Wed, 07 Sep 2016 09:27:09 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id f4si28616966pfk.58.2016.09.07.09.27.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Sep 2016 09:27:09 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-return-93783-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of binutils-return-93783-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-93783-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:to:cc:from:subject:message-id:date :mime-version:content-type; q=dns; s=default; b=G1R/Z41chtcai2hR AUE//8wRbsmJ4s+IYhaguc6kjg0vVIZIAkn1rKj9xdv8DrdI+V8JY+7Oy+XiCe/7 8AHqjNKrDOyiA4H4g/IzrVM5ZXUCPZNZ9LchSE2YOKmN6By4Y0l8f1WeERRjYvCW ulCnBqKowswq3vgBFzaS5S09diM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:to:cc:from:subject:message-id:date :mime-version:content-type; s=default; bh=vU8X1WyESC4rObhAHjVTQD jZEqQ=; b=kkRL1XTju9qO41uCm3ORhxZQQc0Fzft814YQKHvVAq689Rz4Q85zCn 1drOrmdgI3dxG0adpd9pwy5/DTo2/tkOR4DdyYilvOZqpR1geZl8UuMQlvCCbcia qo/PCHrsEXSJpZz2HJQMcXF+FMwKPqH7oLddv+6ElHVhT+iqLi1P4= Received: (qmail 4817 invoked by alias); 7 Sep 2016 16:26:31 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 4692 invoked by uid 89); 7 Sep 2016 16:26:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=Samsung, Automatically, aarch32, family X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Sep 2016 16:26:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1AD4F462; Wed, 7 Sep 2016 09:26:26 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34E713F251; Wed, 7 Sep 2016 09:26:25 -0700 (PDT) To: binutils@sourceware.org Cc: e.menezes@samsung.com, "philipp.tomsich@theobroma-systems.com" , jim.wilson@linaro.org From: "Richard Earnshaw (lists)" Subject: [arm] Automatically enable CRC instructions on supported ARMv8-A CPUs Message-ID: Date: Wed, 7 Sep 2016 17:26:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 When assembling for a named CPU we know whether or not that CPU has the ARMv8-A CRC extension. However, this was not coded into the assembler, requiring the user to explicitly enable this feature. Unfortunately, GCC assumes that we know that CRC is present and so files passed through by the compiler result in errors during assembly. This patch fixes this by introducing a new 'architecture' containing the CRC extension and then adjusting all the ARMv8-A cores that have this feature (everything bar xgene1) to use the new architecture setting. Although I don't have datasheets for all the parts I've enabled this for the xgene2, exynos-m1 and qdf24xx parts since all of these have the feature enabled already in the AArch64 assembler. If this is not correct for AArch32, then please can the relevant maintainers let me know. Tested with some simple smoke tests both using -mcpu= and .cpu directives. include: * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture. gas: * config/tc-arm.h (arm_cpus): Use ARM_ARCH_V8A_CRC for all ARMv8-A CPUs except xgene1. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 73d0531..7c86184 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -25332,17 +25332,17 @@ static const struct arm_cpu_option_table arm_cpus[] = "Cortex-A15"), ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4, "Cortex-A17"), - ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A32"), - ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A35"), - ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A53"), - ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A57"), - ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A72"), - ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Cortex-A73"), ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"), ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16, @@ -25361,10 +25361,10 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"), ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"), ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"), - ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Samsung " \ "Exynos M1"), - ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Qualcomm " "QDF24XX"), @@ -25389,7 +25389,7 @@ static const struct arm_cpu_option_table arm_cpus[] = /* APM X-Gene family. */ ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "APM X-Gene 1"), - ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A_CRC, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "APM X-Gene 2"), { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL } diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 60715cf..feace5c 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -263,6 +263,8 @@ #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) +#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \ + CRC_EXT_ARMV8) #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA) #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \