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[209.132.180.131]) by mx.google.com with ESMTPS id e188si30669684pfg.248.2016.09.07.13.06.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Sep 2016 13:06:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-435441-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-435441-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-435441-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=xB73J6OgSXhmri0q4RMc68sVy5L/tVBje/kGdQ9hFoh2iX Z2T1CvZ6YpJWThb/YL8jwPCy7eRlegKOY6DWfQgxeiY7xad9PxdoByB0N5XZQkGr vMMzGv5BFbnLxZwn2F0rqk52zhDod/0t82+m5wjf2HIvtAUrPC4nHO/3AiVfk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=QN/F9bmsqsWYDN45AeKMtXcthcU=; b=IxuXAwQj+dgxQFNnl941 ZdtHHrJzREN/+th9mSRoAeZ2RO8TBF60614UUQ9g+RogYQRzAvuGaG9xMq8M8E/u F+TGGeicQV4BY7qvv9avrbzo1MHbx2I/LUhQQNA4AUF17nuyT7On0tt9qD4YNAPA hsY2TZg9MxI9Cp6BNzlnNCk= Received: (qmail 15445 invoked by alias); 7 Sep 2016 20:06:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15435 invoked by uid 89); 7 Sep 2016 20:05:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=rl, sk:people, sk:people., sk:christo X-HELO: mail-qt0-f182.google.com Received: from mail-qt0-f182.google.com (HELO mail-qt0-f182.google.com) (209.85.216.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Sep 2016 20:05:49 +0000 Received: by mail-qt0-f182.google.com with SMTP id 11so13097571qtc.0 for ; Wed, 07 Sep 2016 13:05:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=lxiZNlKg1VVVxeKrWTSsbDJRvl1SL0kOBlnrkRWAId8=; b=Bo3ahlCaouXKhDW80wuKjdMrStUjtX1cy/a/r9fcLoN4BKUFbYLTMpR4GgJpQV4vEN S18rn8cUT8T5cTIQM41pLI/xYgpcUG1kdaLw5Ue/GCwIykExt19Fe6kfVuzBoW48dAY2 bDFgiE6TdjoVqNyUHj9FzCTPlf6m49iPJoj0dZZXw/Ju6ZeJ7or4qMDSdyivYriUlUa/ FR+Ps6/ketMYlwVebLWuKTOiiraRsQkr4Jr67mgfApXVEU9mnqb7j13j2B6A69ExFQIC 6QEF2gdrUgE3j89DsMxrsfzMGbUFm3nsNAzQBy6T48WfEK24q5bus0Wpt1RBzIsZPk69 Q7ig== X-Gm-Message-State: AE9vXwNNdvsCK7PnmZUjQ3mdvh0+tfULoOOO86XBVlNlJD8mjWgOMYBLSPidn0Xv4eUl+W3yvdpfoQvqYrlwaKXN X-Received: by 10.200.50.152 with SMTP id z24mr29957225qta.50.1473278746938; Wed, 07 Sep 2016 13:05:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.21.102 with HTTP; Wed, 7 Sep 2016 13:05:46 -0700 (PDT) From: Christophe Lyon Date: Wed, 7 Sep 2016 22:05:46 +0200 Message-ID: Subject: [ARM] PR 67591 ARM v8 Thumb IT blocks are deprecated To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes Hi, The attached patch is a first part to solve PR 67591: it removes several occurrences of "IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8" messages in the gcc/g++/libstdc++/fortran testsuites. It does not remove them all yet. This patch only modifies the *cmp_and, *cmp_ior, *ior_scc_scc, *ior_scc_scc_cmp, *and_scc_scc and *and_scc_scc_cmp patterns. Additional work is required in sub_shiftsi etc, at least. I've started looking at these, but I decided I could already post this self-contained patch to check if this implementation is OK. Regarding *cmp_and and *cmp_ior patterns, the addition of the enabled_for_depr_it attribute is aggressive in the sense that it keeps only the alternatives with 'l' and 'Py' constraints, while in some cases the constraints could be relaxed. Indeed, these 2 patterns can swap their input comparisons, meaning that any of them can be emitted in the IT-block, and is thus subject to the ARMv8 deprecation. The generated code is possibly suboptimal in the cases where the operands are not swapped, since 'r' could be used. Cross-tested on arm-none-linux-gnueabihf with -mthumb/-march=armv8-a and --with-cpu=cortex-a57 --with-mode=thumb, showing only improvements: http://people.linaro.org/~christophe.lyon/cross-validation/gcc-test-patches/239850-depr-it-4/report-build-info.html Bootstrapped OK on armv8l HW. Is this OK? Thanks, Christophe 2016-09-05 Christophe Lyon PR target/67591 * config/arm/arm.md (*cmp_and): Add enabled_for_depr_it attribute. (*cmp_ior): Likewise. (*ior_scc_scc): Add alternative for enabled_for_depr_it attribute. (*ior_scc_scc_cmp): Likewise. (*and_scc_scc): Likewise. (*and_scc_scc_cmp): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 318db75..0374bdd 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -9340,6 +9340,7 @@ [(set_attr "conds" "set") (set_attr "predicable" "no") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9422,6 +9423,7 @@ " [(set_attr "conds" "set") (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr "enabled_for_depr_it" "yes,no,no,no,no,no,no,no,no") (set_attr_alternative "length" [(const_int 6) (const_int 8) @@ -9444,13 +9446,13 @@ ) (define_insn_and_split "*ior_scc_scc" - [(set (match_operand:SI 0 "s_register_operand" "=Ts") + [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") (ior:SI (match_operator:SI 3 "arm_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_add_operand" "rIL")]) + [(match_operand:SI 1 "s_register_operand" "r,l") + (match_operand:SI 2 "arm_add_operand" "rIL,lPy")]) (match_operator:SI 6 "arm_comparison_operator" - [(match_operand:SI 4 "s_register_operand" "r") - (match_operand:SI 5 "arm_add_operand" "rIL")]))) + [(match_operand:SI 4 "s_register_operand" "r,l") + (match_operand:SI 5 "arm_add_operand" "rIL,lPy")]))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) @@ -9469,6 +9471,7 @@ DOM_CC_X_OR_Y), CC_REGNUM);" [(set_attr "conds" "clob") + (set_attr "enabled_for_depr_it" "no,yes") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9478,13 +9481,13 @@ (define_insn_and_split "*ior_scc_scc_cmp" [(set (match_operand 0 "dominant_cc_register" "") (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_add_operand" "rIL")]) + [(match_operand:SI 1 "s_register_operand" "r,l") + (match_operand:SI 2 "arm_add_operand" "rIL,lPy")]) (match_operator:SI 6 "arm_comparison_operator" - [(match_operand:SI 4 "s_register_operand" "r") - (match_operand:SI 5 "arm_add_operand" "rIL")])) + [(match_operand:SI 4 "s_register_operand" "r,l") + (match_operand:SI 5 "arm_add_operand" "rIL,lPy")])) (const_int 0))) - (set (match_operand:SI 7 "s_register_operand" "=Ts") + (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts") (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] "TARGET_32BIT" @@ -9499,18 +9502,19 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") + (set_attr "enabled_for_depr_it" "no,yes") (set_attr "length" "16") (set_attr "type" "multiple")] ) (define_insn_and_split "*and_scc_scc" - [(set (match_operand:SI 0 "s_register_operand" "=Ts") + [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") (and:SI (match_operator:SI 3 "arm_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_add_operand" "rIL")]) + [(match_operand:SI 1 "s_register_operand" "r,l") + (match_operand:SI 2 "arm_add_operand" "rIL,lPy")]) (match_operator:SI 6 "arm_comparison_operator" - [(match_operand:SI 4 "s_register_operand" "r") - (match_operand:SI 5 "arm_add_operand" "rIL")]))) + [(match_operand:SI 4 "s_register_operand" "r,l") + (match_operand:SI 5 "arm_add_operand" "rIL,lPy")]))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) @@ -9531,6 +9535,7 @@ DOM_CC_X_AND_Y), CC_REGNUM);" [(set_attr "conds" "clob") + (set_attr "enabled_for_depr_it" "no,yes") (set_attr "length" "16") (set_attr "type" "multiple")] ) @@ -9540,13 +9545,13 @@ (define_insn_and_split "*and_scc_scc_cmp" [(set (match_operand 0 "dominant_cc_register" "") (compare (and:SI (match_operator:SI 3 "arm_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_add_operand" "rIL")]) + [(match_operand:SI 1 "s_register_operand" "r,l") + (match_operand:SI 2 "arm_add_operand" "rIL,lPy")]) (match_operator:SI 6 "arm_comparison_operator" - [(match_operand:SI 4 "s_register_operand" "r") - (match_operand:SI 5 "arm_add_operand" "rIL")])) + [(match_operand:SI 4 "s_register_operand" "r,l") + (match_operand:SI 5 "arm_add_operand" "rIL,lPy")])) (const_int 0))) - (set (match_operand:SI 7 "s_register_operand" "=Ts") + (set (match_operand:SI 7 "s_register_operand" "=Ts,Ts") (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] "TARGET_32BIT" @@ -9561,6 +9566,7 @@ (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] "" [(set_attr "conds" "set") + (set_attr "enabled_for_depr_it" "no,yes") (set_attr "length" "16") (set_attr "type" "multiple")] )