| Message ID | 20231220-sa8295p-gpu-v2-7-4763246b72c0@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: sa8295p: Enable GPU | expand |
On Wed, Dec 27, 2023 at 02:09:47AM +0100, Konrad Dybcio wrote: > On 22.12.2023 05:39, Bjorn Andersson wrote: > > With the necessary support in place for supplying VDD_GFX from the > > MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU > > and the GPU on the SA8295P ADP. > > > > Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> > > --- > [...] > > > +&gpucc { > > + vdd-gfx-supply = <&vdd_gfx>; > > + status = "okay"; > > +}; > Already enabled > No, we're disabling these in sa8540p.dtsi, so they need to be re-enabled here. I don't remember if it's because the attempt to bring up gfx.lvl or if it's the attempt to operate the GPU components without adequate VDD_GFX, that is causing the issue...but either way, we don't survive boot. It's possible that we could move the max20411 up to sa8540p.dtsi to avoid the intermediate disable, but I'm not confident that it's "part of the platform"... Regards, Bjorn > > + > > +&gmu { > > + status = "okay"; > > +}; > > + > > +&gpu { > > + status = "okay"; > > + > > + zap-shader { > > + memory-region = <&gpu_mem>; > > + firmware-name = "qcom/sa8295p/a690_zap.mbn"; > > + }; > > +}; > > + > > +&gpu_smmu { > > + status = "okay"; > > +}; > Already enabled > > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 14327c697116..304c8d79bd31 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { }; }; +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mbn"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; };
With the necessary support in place for supplying VDD_GFX from the MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU and the GPU on the SA8295P ADP. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)