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[2/4] PCI: qcom: Cache last icc bandwidth

Message ID 20231227-topic-8280_pcie-v1-2-095491baf9e4@linaro.org
State New
Headers show
Series Qualcomm PCIe RC shutdown & reinit | expand

Commit Message

Konrad Dybcio Dec. 27, 2023, 10:17 p.m. UTC
In preparation for shutting down the RC, cache the last interconnect
bandwidth vote to allow for icc tag setting.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1c5ab8c4ff39..a02dc197c495 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -240,6 +240,7 @@  struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	struct icc_path *icc_mem;
+	u32 last_bw;
 	const struct qcom_pcie_cfg *cfg;
 	struct dentry *debugfs;
 	bool suspended;
@@ -1387,6 +1388,8 @@  static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
 		return ret;
 	}
 
+	pcie->last_bw = QCOM_PCIE_LINK_SPEED_TO_BW(1);
+
 	return 0;
 }
 
@@ -1415,6 +1418,8 @@  static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
 		dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
 			ret);
 	}
+
+	pcie->last_bw = width * QCOM_PCIE_LINK_SPEED_TO_BW(speed);
 }
 
 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
@@ -1578,6 +1583,8 @@  static int qcom_pcie_suspend_noirq(struct device *dev)
 		return ret;
 	}
 
+	pcie->last_bw = kBps_to_icc(1);
+
 	/*
 	 * Turn OFF the resources only for controllers without active PCIe
 	 * devices. For controllers with active devices, the resources are kept