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[PULL,40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry

Message ID 20240111110505.1563291-41-peter.maydell@linaro.org
State Accepted
Commit 3b32140e706b586a0b17050f99ffc812c8849bd0
Headers show
Series [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 | expand

Commit Message

Peter Maydell Jan. 11, 2024, 11:05 a.m. UTC 
We already print various lines of information when we take an
exception, including the ELR and (if relevant) the FAR. Now
that FEAT_NV means that we might report something other than
the old PSTATE to the guest as the SPSR, it's worth logging
this as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
 target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4550ff7ffde..dc8f14f4331 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11416,6 +11416,7 @@  static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     }
     env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
 
+    qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode);
     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
                   env->elr_el[new_el]);