[PULL,34/36] MAINTAINERS: Update Raphael Norwitz email

From: Raphael Norwitz <raphael.norwitz@nutanix.com>

Received-SPF: pass (google.com: domain of
 qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as
 permitted sender) client-ip=209.51.188.17;
From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org,
 qemu-arm@nongnu.org, Raphael Norwitz <raphael.norwitz@nutanix.com>,
	=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email
Date: Fri, 19 Jan 2024 12:35:03 +0100
Message-ID: <20240119113507.31951-35-philmd@linaro.org>
In-Reply-To: <20240119113507.31951-1-philmd@linaro.org>
References: <20240119113507.31951-1-philmd@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Received-SPF: pass client-ip=2a00:1450:4864:20::42b;
 envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
 DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
 RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,
 T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org

Message ID	20240119113507.31951-35-philmd@linaro.org
State	Accepted
Commit	1c50d026d518eb4549084f14825648afe8fc2a7c
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Raphael Norwitz <raphael.norwitz@nutanix.com>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email Date: Fri, 19 Jan 2024 12:35:03 +0100 Message-ID: <20240119113507.31951-35-philmd@linaro.org> In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/36] hw/timer/hpet: Convert DPRINTF to trace events \| expand [PULL,01/36] hw/timer/hpet: Convert DPRINTF to trace events [PULL,02/36] backends/cryptodev: Do not ignore throttle/backends Errors [PULL,03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels [PULL,04/36] accel: Do not set CPUState::can_do_io in non-TCG accels [PULL,05/36] target/xtensa: use generic instruction breakpoint infrastructure [PULL,06/36] tests/tcg/xtensa: add icount/ibreak priority test [PULL,07/36] accel/tcg: Remove unused tb_invalidate_phys_addr() [PULL,08/36] accel/tcg: Remove tb_invalidate_phys_page() from system emulation [PULL,09/36] target/alpha: Extract clk_helper.c from sys_helper.c [PULL,10/36] target/alpha: Only build sys_helper.c on system emulation [PULL,11/36] system/cpu-timers: Have icount_configure() return a boolean [PULL,12/36] system/cpu-timers: Introduce ICountMode enumerator [PULL,13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED [PULL,14/36] util/async: Only call icount_notify_exit() if icount is enabled [PULL,15/36] target/sh4: Deprecate the shix machine [PULL,16/36] hw/block: Deprecate the TC58128 block device [PULL,17/36] hw/i386/pc_piix: Make piix_intx_routing_notifier_xen() more device independent [PULL,18/36] hw/pflash: refactor pflash_data_write() [PULL,19/36] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p [PULL,20/36] hw/pflash: implement update buffer for block writes [PULL,21/36] system/replay: Restrict icount to system emulation [PULL,22/36] system/watchpoint: Move TCG specific code to accel/tcg/ [PULL,23/36] cpus: Restrict 'start-powered-off' property to system emulation [PULL,24/36] accel: Rename accel_init_ops_interfaces() to include 'system' [PULL,25/36] hw/core/cpu: Rename cpu_class_init() to include 'common' [PULL,26/36] hw/s390x: Rename cpu_class_init() to include 'sclp' [PULL,27/36] target/i386: Rename tcg_cpu_FOO() to include 'x86' [PULL,28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' [PULL,29/36] hw/scsi/esp-pci: use correct address register for PCI DMA transfers [PULL,30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources [PULL,31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt [PULL,32/36] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued [PULL,33/36] hw/elf_ops: Ignore loadable segments with zero size [PULL,34/36] MAINTAINERS: Update Raphael Norwitz email [PULL,35/36] MAINTAINERS: Update hw/core/cpu.c entry [PULL,36/36] configure: Add linux header compile support for LoongArch

[PULL,34/36] MAINTAINERS: Update Raphael Norwitz email

Commit Message

Patch