diff mbox series

[v4,3/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock

Message ID 20240122-ipq5332-nsscc-v4-3-19fa30019770@quicinc.com
State New
Headers show
Series Add NSS clock controller support for Qualcomm IPQ5332 | expand

Commit Message

Kathiravan Thirumoorthy Jan. 22, 2024, 5:56 a.m. UTC 
Add the definition for GPLL0_OUT_AUX clock.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Andrew Lunn Jan. 25, 2024, 8:07 p.m. UTC | #1 
On Mon, Jan 22, 2024 at 11:26:59AM +0530, Kathiravan Thirumoorthy wrote:
> Add the definition for GPLL0_OUT_AUX clock.

The commit message should answer the question "Why?". Why are you
adding this clock? What consumes it?

       Andrew
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..24486eb47ed8 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -179,6 +179,7 @@ 
 #define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
 #define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
 #define GCC_USB0_PIPE_CLK_SRC				172
+#define GPLL0_OUT_AUX					173
 
 #define GCC_ADSS_BCR					0
 #define GCC_ADSS_PWM_CLK_ARES				1