diff mbox series

[v2] riscv: dts: sophgo: add watchdog dt node for CV1800

Message ID DM6PR20MB2316366FC9ADCBC7B6E9C289AB7A2@DM6PR20MB2316.namprd20.prod.outlook.com
State New
Headers show
Series [v2] riscv: dts: sophgo: add watchdog dt node for CV1800 | expand

Commit Message

AnnanLiu Jan. 25, 2024, 9:46 a.m. UTC 
Add the watchdog device tree node to cv1800 SoC.

Signed-off-by: AnnanLiu <annan.liu.xdu@outlook.com>
---
This patch depends on the clk driver and reset driver.
Clk driver link:
https://lore.kernel.org/all/IA1PR20MB49539CDAD9A268CBF6CA184BBB9FA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reset driver link:
https://lore.kernel.org/all/20231113005503.2423-1-jszhang@kernel.org/

Changes since v1:
- Change the name of the watchdog from watchdog0 to watchdog.
- Change the status of watchdog.
v1 link:
https://lore.kernel.org/all/DM6PR20MB23160B8499CC2BFDAE6FCACDAB9EA@DM6PR20MB2316.namprd20.prod.outlook.com/


 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts |  4 ++++
 arch/riscv/boot/dts/sophgo/cv1800b.dtsi          | 16 ++++++++++++++++
 2 files changed, 20 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
index 3af9e34b3bc7..75469161bfff 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
+++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
@@ -36,3 +36,7 @@  &osc {
 &uart0 {
 	status = "okay";
 };
+
+&watchdog {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index aec6401a467b..03ca32cd37b6 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -1,6 +1,7 @@ 
 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
 /*
  * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2024 Annan Liu <annan.liu.xdu@outlook.com>
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -103,6 +104,21 @@  uart4: serial@41c0000 {
 			status = "disabled";
 		};
 
+		watchdog: watchdog@3010000{
+			compatible = "snps,dw-wdt";
+			reg = <0x3010000 0x100>;
+			interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pclk>;
+			resets = <&rst RST_WDT>;
+			status = "disabled";
+		};
+
+		pclk: pclk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
 		plic: interrupt-controller@70000000 {
 			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
 			reg = <0x70000000 0x4000000>;