@@ -1501,6 +1501,18 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
+static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
+ .fifosize = 64,
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .clk_div = 4,
+ .high_speed = true,
+ .clk_from_cmu = true,
+ .has_loopback = true,
+ .use_32bit_io = true,
+ .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
.fifosize = 64,
.rx_lvl_offset = 15,
@@ -1556,6 +1568,10 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
.compatible = "samsung,exynosautov9-spi",
.data = &exynosautov9_spi_port_config,
},
+ {
+ .compatible = "google,gs101-spi",
+ .data = &gs101_spi_port_config,
+ },
{
.compatible = "tesla,fsd-spi",
.data = &fsd_spi_port_config,
Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)