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[PULL,35/36] target/arm: Fix incorrect aa64_tidcp1 feature check

Message ID 20240126143341.2101237-36-peter.maydell@linaro.org
State Accepted
Commit ee0a2e3c9d2991a11c13ffadb15e4d0add43c257
Headers show
Series [PULL,01/36] target/xtensa: fix OOB TLB entry access | expand

Commit Message

Peter Maydell Jan. 26, 2024, 2:33 p.m. UTC 
A typo in the implementation of isar_feature_aa64_tidcp1() means we
were checking the field in the wrong ID register, so we might have
provided the feature on CPUs that don't have it and not provided
it on CPUs that should have it. Correct this bug.

Cc: qemu-stable@nongnu.org
Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1"
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240123160333.958841-1-peter.maydell@linaro.org
---
 target/arm/cpu-features.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 028795ff23f..7567854db63 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -773,7 +773,7 @@  static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
 
 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
 {
-    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
 }
 
 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)