@@ -182,8 +182,6 @@ static int hppvi_index(GICv3CPUState *cs)
* priority than the highest priority list register at every
* callsite of HighestPriorityVirtualInterrupt; we check it here.)
*/
- ARMCPU *cpu = ARM_CPU(cs->cpu);
- CPUARMState *env = &cpu->env;
int idx = -1;
int i;
/* Note that a list register entry with a priority of 0xff will
@@ -230,7 +228,7 @@ static int hppvi_index(GICv3CPUState *cs)
* fails the priority check here. vLPIs are only considered
* when we are in Non-Secure state.
*/
- if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) {
+ if (cs->hppvlpi.prio < prio && !arm_is_secure(cpu_env(cs->cpu))) {
if (cs->hppvlpi.grp == GICV3_G0) {
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) {
return HPPVI_INDEX_VLPI;
@@ -931,8 +929,7 @@ void gicv3_cpuif_update(GICv3CPUState *cs)
/* Tell the CPU about its highest priority pending interrupt */
int irqlevel = 0;
int fiqlevel = 0;
- ARMCPU *cpu = ARM_CPU(cs->cpu);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs->cpu);
g_assert(bql_locked());
@@ -15,8 +15,5 @@
void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
{
- ARMCPU *arm_cpu = ARM_CPU(cpu);
- CPUARMState *env = &arm_cpu->env;
-
- env->gicv3state = (void *)s;
+ cpu_env(cpu)->gicv3state = (void *)s;
};
@@ -53,8 +53,7 @@
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
if (is_a64(env)) {
env->pc = value;
@@ -67,8 +66,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
static vaddr arm_cpu_get_pc(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
if (is_a64(env)) {
return env->pc;
@@ -996,19 +994,15 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
cpu_synchronize_state(cs);
- return arm_cpu_data_is_big_endian(env);
+ return arm_cpu_data_is_big_endian(cpu_env(cs));
}
#endif
static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
{
- ARMCPU *ac = ARM_CPU(cpu);
- CPUARMState *env = &ac->env;
+ CPUARMState *env = cpu_env(cpu);
bool sctlr_b;
if (is_a64(env)) {
@@ -2435,10 +2429,7 @@ static Property arm_cpu_properties[] = {
static const gchar *arm_gdb_arch_name(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
+ if (arm_feature(cpu_env(cs), ARM_FEATURE_IWMMXT)) {
return "iwmmxt";
}
return "arm";
@@ -468,8 +468,7 @@ void arm_debug_excp_handler(CPUState *cs)
* Called by core code when a watchpoint or breakpoint fires;
* need to check which one and raise the appropriate exception.
*/
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
if (wp_hit) {
@@ -757,9 +756,6 @@ void hw_breakpoint_update_all(ARMCPU *cpu)
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
/*
* In BE32 system mode, target memory is stored byteswapped (on a
* little-endian host system), and by the time we reach here (via an
@@ -767,7 +763,7 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
* to account for that, which means that watchpoints will not match.
* Undo the adjustment here.
*/
- if (arm_sctlr_b(env)) {
+ if (arm_sctlr_b(cpu_env(cs))) {
if (len == 1) {
addr ^= 3;
} else if (len == 2) {
@@ -40,8 +40,7 @@ typedef struct RegisterSysregXmlParam {
int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
if (n < 16) {
/* Core integer register. */
@@ -61,8 +60,7 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
uint32_t tmp;
tmp = ldl_p(mem_buf);
@@ -24,8 +24,7 @@
int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
if (n < 31) {
/* Core integer register. */
@@ -45,8 +44,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
uint64_t tmp;
tmp = ldq_p(mem_buf);
@@ -10902,8 +10902,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
* PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
*/
uint32_t addr, mask;
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
switch (cs->exception_index) {
case EXCP_UDEF:
@@ -10981,8 +10980,7 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
uint32_t addr;
uint32_t mask;
int new_mode;
@@ -11481,8 +11479,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
#ifdef CONFIG_TCG
static void tcg_handle_semihosting(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
if (is_a64(env)) {
qemu_log_mask(CPU_LOG_INT,
@@ -1006,8 +1006,7 @@ void hvf_kick_vcpu_thread(CPUState *cpu)
static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
uint32_t syndrome)
{
- ARMCPU *arm_cpu = ARM_CPU(cpu);
- CPUARMState *env = &arm_cpu->env;
+ CPUARMState *env = cpu_env(cpu);
cpu->exception_index = excp;
env->exception.target_el = 1;
@@ -1485,8 +1484,7 @@ static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
{
- ARMCPU *arm_cpu = ARM_CPU(cpu);
- CPUARMState *env = &arm_cpu->env;
+ CPUARMState *env = cpu_env(cpu);
trace_hvf_sysreg_write(reg,
SYSREG_OP0(reg),
@@ -2152,8 +2150,7 @@ static void hvf_put_gdbstub_debug_registers(CPUState *cpu)
*/
static void hvf_put_guest_debug_registers(CPUState *cpu)
{
- ARMCPU *arm_cpu = ARM_CPU(cpu);
- CPUARMState *env = &arm_cpu->env;
+ CPUARMState *env = cpu_env(cpu);
hv_return_t r = HV_SUCCESS;
int i;
@@ -2207,8 +2204,7 @@ static void hvf_arch_set_traps(void)
void hvf_arch_update_guest_debug(CPUState *cpu)
{
- ARMCPU *arm_cpu = ARM_CPU(cpu);
- CPUARMState *env = &arm_cpu->env;
+ CPUARMState *env = cpu_env(cpu);
/* Check whether guest debugging is enabled */
cpu->accel->guest_debug_enabled = cpu->singlestep_enabled ||
@@ -1958,8 +1958,7 @@ int kvm_arch_destroy_vcpu(CPUState *cs)
/* Callers must hold the iothread mutex lock */
static void kvm_inject_arm_sea(CPUState *c)
{
- ARMCPU *cpu = ARM_CPU(c);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(c);
uint32_t esr;
bool same_el;
@@ -3528,8 +3528,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
MemTxAttrs *attrs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cpu_env(cs);
ARMMMUIdx mmu_idx = arm_mmu_idx(env);
ARMSecuritySpace ss = arm_security_space(env);
S1Translate ptw = {
@@ -102,8 +102,6 @@ void aa32_max_features(ARMCPU *cpu)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
bool ret = false;
/*
@@ -115,7 +113,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
* currently active exception).
*/
if (interrupt_request & CPU_INTERRUPT_HARD
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
+ && (armv7m_nvic_can_take_pending_exception(cpu_env(cs)->nvic))) {
cs->exception_index = EXCP_IRQ;
cc->tcg_ops->do_interrupt(cs);
ret = true;
@@ -9326,7 +9326,6 @@ static void arm_post_translate_insn(DisasContext *dc)
static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- CPUARMState *env = cpu_env(cpu);
uint32_t pc = dc->base.pc_next;
unsigned int insn;
@@ -9356,7 +9355,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
}
dc->pc_curr = pc;
- insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
+ insn = arm_ldl_code(cpu_env(cpu), &dc->base, pc, dc->sctlr_b);
dc->insn = insn;
dc->base.pc_next = pc + 4;
disas_arm_insn(dc, insn);
Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/intc/arm_gicv3_cpuif.c | 7 ++----- hw/intc/arm_gicv3_cpuif_common.c | 5 +---- target/arm/cpu.c | 19 +++++-------------- target/arm/debug_helper.c | 8 ++------ target/arm/gdbstub.c | 6 ++---- target/arm/gdbstub64.c | 6 ++---- target/arm/helper.c | 9 +++------ target/arm/hvf/hvf.c | 12 ++++-------- target/arm/kvm.c | 3 +-- target/arm/ptw.c | 3 +-- target/arm/tcg/cpu32.c | 4 +--- target/arm/tcg/translate.c | 3 +-- 12 files changed, 25 insertions(+), 60 deletions(-)