diff mbox series

[23/33] target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

Message ID 20240129233043.34558-24-richard.henderson@linaro.org
State Superseded
Headers show
Series hw/core: Introduce CPUClass hook for mmu_index | expand

Commit Message

Richard Henderson Jan. 29, 2024, 11:30 p.m. UTC 
Use the target-specific function name in preference
to the generic name.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_helper.c    | 4 ++--
 target/riscv/op_helper.c     | 4 ++--
 target/riscv/vector_helper.c | 9 +++++----
 3 files changed, 9 insertions(+), 8 deletions(-)

Comments

Alistair Francis Jan. 30, 2024, 12:41 a.m. UTC | #1 
On Tue, Jan 30, 2024 at 9:36 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the target-specific function name in preference
> to the generic name.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c    | 4 ++--
>  target/riscv/op_helper.c     | 4 ++--
>  target/riscv/vector_helper.c | 9 +++++----
>  3 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 15f87ecdb0..b6b23b7d03 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -106,7 +106,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
>  #else
>      flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
>
> -    flags |= cpu_mmu_index(env, 0);
> +    flags |= riscv_env_mmu_index(env, 0);
>      fs = get_field(env->mstatus, MSTATUS_FS);
>      vs = get_field(env->mstatus, MSTATUS_VS);
>
> @@ -1200,7 +1200,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>      CPURISCVState *env = &cpu->env;
>      hwaddr phys_addr;
>      int prot;
> -    int mmu_idx = cpu_mmu_index(&cpu->env, false);
> +    int mmu_idx = riscv_env_mmu_index(&cpu->env, false);
>
>      if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
>                               true, env->virt_enabled, true)) {
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 5355225d56..f414aaebdb 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -157,7 +157,7 @@ void helper_cbo_zero(CPURISCVState *env, target_ulong address)
>  {
>      RISCVCPU *cpu = env_archcpu(env);
>      uint16_t cbozlen = cpu->cfg.cboz_blocksize;
> -    int mmu_idx = cpu_mmu_index(env, false);
> +    int mmu_idx = riscv_env_mmu_index(env, false);
>      uintptr_t ra = GETPC();
>      void *mem;
>
> @@ -205,7 +205,7 @@ static void check_zicbom_access(CPURISCVState *env,
>                                  uintptr_t ra)
>  {
>      RISCVCPU *cpu = env_archcpu(env);
> -    int mmu_idx = cpu_mmu_index(env, false);
> +    int mmu_idx = riscv_env_mmu_index(env, false);
>      uint16_t cbomlen = cpu->cfg.cbom_blocksize;
>      void *phost;
>      int ret;
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c1c3a4d1ea..fe0d5d053c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -113,14 +113,15 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
>  {
>      target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
>      target_ulong curlen = MIN(pagelen, len);
> +    int mmu_index = riscv_env_mmu_index(env, false);
>
>      probe_access(env, adjust_addr(env, addr), curlen, access_type,
> -                 cpu_mmu_index(env, false), ra);
> +                 mmu_index, ra);
>      if (len > curlen) {
>          addr += curlen;
>          curlen = len - curlen;
>          probe_access(env, adjust_addr(env, addr), curlen, access_type,
> -                     cpu_mmu_index(env, false), ra);
> +                     mmu_index, ra);
>      }
>  }
>
> @@ -464,6 +465,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
>      uint32_t esz = 1 << log2_esz;
>      uint32_t vma = vext_vma(desc);
>      target_ulong addr, offset, remain;
> +    int mmu_index = riscv_env_mmu_index(env, false);
>
>      /* probe every access */
>      for (i = env->vstart; i < env->vl; i++) {
> @@ -478,8 +480,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
>              remain = nf << log2_esz;
>              while (remain > 0) {
>                  offset = -(addr | TARGET_PAGE_MASK);
> -                host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
> -                                         cpu_mmu_index(env, false));
> +                host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_index);
>                  if (host) {
>  #ifdef CONFIG_USER_ONLY
>                      if (!page_check_range(addr, offset, PAGE_READ)) {
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 15f87ecdb0..b6b23b7d03 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -106,7 +106,7 @@  void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 #else
     flags = FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv);
 
-    flags |= cpu_mmu_index(env, 0);
+    flags |= riscv_env_mmu_index(env, 0);
     fs = get_field(env->mstatus, MSTATUS_FS);
     vs = get_field(env->mstatus, MSTATUS_VS);
 
@@ -1200,7 +1200,7 @@  hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     CPURISCVState *env = &cpu->env;
     hwaddr phys_addr;
     int prot;
-    int mmu_idx = cpu_mmu_index(&cpu->env, false);
+    int mmu_idx = riscv_env_mmu_index(&cpu->env, false);
 
     if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
                              true, env->virt_enabled, true)) {
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 5355225d56..f414aaebdb 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -157,7 +157,7 @@  void helper_cbo_zero(CPURISCVState *env, target_ulong address)
 {
     RISCVCPU *cpu = env_archcpu(env);
     uint16_t cbozlen = cpu->cfg.cboz_blocksize;
-    int mmu_idx = cpu_mmu_index(env, false);
+    int mmu_idx = riscv_env_mmu_index(env, false);
     uintptr_t ra = GETPC();
     void *mem;
 
@@ -205,7 +205,7 @@  static void check_zicbom_access(CPURISCVState *env,
                                 uintptr_t ra)
 {
     RISCVCPU *cpu = env_archcpu(env);
-    int mmu_idx = cpu_mmu_index(env, false);
+    int mmu_idx = riscv_env_mmu_index(env, false);
     uint16_t cbomlen = cpu->cfg.cbom_blocksize;
     void *phost;
     int ret;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c1c3a4d1ea..fe0d5d053c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -113,14 +113,15 @@  static void probe_pages(CPURISCVState *env, target_ulong addr,
 {
     target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
     target_ulong curlen = MIN(pagelen, len);
+    int mmu_index = riscv_env_mmu_index(env, false);
 
     probe_access(env, adjust_addr(env, addr), curlen, access_type,
-                 cpu_mmu_index(env, false), ra);
+                 mmu_index, ra);
     if (len > curlen) {
         addr += curlen;
         curlen = len - curlen;
         probe_access(env, adjust_addr(env, addr), curlen, access_type,
-                     cpu_mmu_index(env, false), ra);
+                     mmu_index, ra);
     }
 }
 
@@ -464,6 +465,7 @@  vext_ldff(void *vd, void *v0, target_ulong base,
     uint32_t esz = 1 << log2_esz;
     uint32_t vma = vext_vma(desc);
     target_ulong addr, offset, remain;
+    int mmu_index = riscv_env_mmu_index(env, false);
 
     /* probe every access */
     for (i = env->vstart; i < env->vl; i++) {
@@ -478,8 +480,7 @@  vext_ldff(void *vd, void *v0, target_ulong base,
             remain = nf << log2_esz;
             while (remain > 0) {
                 offset = -(addr | TARGET_PAGE_MASK);
-                host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
-                                         cpu_mmu_index(env, false));
+                host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmu_index);
                 if (host) {
 #ifdef CONFIG_USER_ONLY
                     if (!page_check_range(addr, offset, PAGE_READ)) {